Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 888

External Port DMA Control Registers (DMACx)
Table A-32. External Port DMA Register Bit Descriptions (RW) (Cont'd)
Bit Name
9 TLEN
11–10 Reserved
12 INTIRT
15–13 Reserved
17–16 (RO) DFS
19–18 Reserved
20 (RO) DMAS
21 (RO) CHS
22 (RO) TLS
23 (RO) WBS
24 (RO) EXTS
A-62
www.BDTIC.com/ADI
Description
Scatter/Gather (Tap List) DMA Enable.
0 = Disables the tap list based scatter/gather DMA
1 = Enables the tap list based scatter/gather DMA
Internal DMA Completion Interrupt (Control).
0 = Interrupt on access completion (internal/external DMA com-
pletion depending on external read/write)
1 = Interrupt on internal DMA completion
This bit is provided for backward compatibility with older
SHARC processors.
DMA FIFO Status.
00 = FIFO Empty
01 = FIFO Partially Full
11 = FIFO Full
10 = Reserved
DMA Transfer Status.
0 = DMA idle
1 = DMA in progress
DMA Chaining Status.
0 = DMA chain loading is not active
1 = DMA chain loading is active
TAP List Loading Status.
1 = TAP list loading is active
0 = TAP list loading is not active
Delay Line Write Pointer Write Back Status.
0 = Write pointer write back is not active
1 = Write pointer write back is active
DMA External Interface Status.
0 = DMA external interface does not have any access pending
1 = DMA external interface has access pending
ADSP-214xx SHARC Processor Hardware Reference