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ADF7021-V
REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER
AGC_CLK_DIVIDE
GD6
GD5
GD4
GD3
0
0
0
0
0
0
0
0
...
...
...
...
1
1
1
1
•
Baseband offset clock frequency (BBOS CLK) must be
greater than 1 MHz and less than 2 MHz, where
BBOS CLK = (XTAL/BBOS_CLK_DIVIDE)
•
Set the demodulator clock (DEMOD CLK) such that
2 MHz ≤ DEMOD CLK ≤ 15 MHz, where
DEMOD CLK = (XTAL/DEMOD_CLK_DIVIDE)
•
For 2FSK/3FSK, the clock/data recovery frequency (CDR
CLK) must be within 2% of (32 × data rate). For 4FSK, the
CDR CLK must be within 2% of (32 × symbol rate).
CDR CLK = (DEMOD CLK/CDR_CLK_DIVIDE)
SEQ_CLK_DIVIDE
SK8
SK7
...
SK3
...
0
0
0
...
0
0
0
...
.
.
.
...
1
1
1
...
1
1
1
GD2
GD1
AGC_CLK_DIVIDE
0
0
INVALID
0
1
1
...
...
...
1
1
63
Figure 65. Register 3—Transmit/Receive Clock Register Map
CDR_CLK_DIVIDE
SK2
SK1
SEQ_CLK_DIVIDE
0
1
1
1
0
2
.
.
.
1
0
254
1
1
255
FS8
FS7
...
FS3
FS2
0
0
...
0
0
0
0
...
0
1
.
.
...
.
.
1
1
...
1
1
1
1
...
1
1
•
The sequencer clock (SEQ CLK) supplies the clock to the
digital receive block. It should be as close to 100 kHz as
possible.
SEQ CLK = (XTAL/SEQ_CLK_DIVIDE)
•
The time allowed for each AGC step to settle is determined
by the AGC update rate. It should be set close to 3 kHz.
AGC Update Rate (Hz) = (SEQ CLK/AGC_CLK_DIVIDE)
Rev. 0 | Page 48 of 60
DEMOD_CLK_
ADDRESS
DIVIDE
BK2
BK1
BBOS_CLK_DIVIDE
0
0
4
0
1
8
1
0
16
1
1
32
OK4
OK3
OK2
OK1
DEMOD_CLK_DIVIDE
0
0
0
0
INVALID
0
0
0
1
1
...
...
...
...
...
1
1
1
1
15
FS1
CDR_CLK_ DIVIDE
1
1
0
2
.
.
0
254
1
255
BITS
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