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(hardware reset) immediately after reset, timing parameter cannot be met,
causing data loss. The DDR2 device must be re-initialized and the DDR2
DLL must be re locked to use the DDR2 again.
Running reset (
controller.
Disabling the Controller
If the DDR2 interface is not used, the following bits should be config-
ured. This is required get maximum power reduction.
• In the
DDR2CTL0
DIS_DDR2CLK1
I/O pads.
• In the
DDR2PADCTL0
register (bits 9 and 19), set (=1) all the
pad receivers.
Initialization Sequence
After the
DDR2PSS
starts the power-up initialization sequence which occurs in the following
order. Note that this procedure is performed by the DDR2 controller and
user intervention is not required.
1. Brings
DDR2CKE
2. Wait a minimum of 400 ns (with
3. Issue a precharge all command. Wait t
4. Issue a load EMR(2) command. Wait t
5. Issue a load EMR(3) command. Wait t
6. Issue a load EMR command. Wait t
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
pin as an input) does not reset the DDR2
RESETOUT
register, set (=1) the following bits:
and
DIS_DDR2CKE
register (bits 9, 19 and 29) and
bit is set in the
DDR2CTL0
high, drive a NOP command.
to disable the controller and its
bits to power-down the
PWD
register, the DDR2 controller
or
commands).
NOP
DESELECT
period.
RPA
period.
MRD
period.
MRD
period.
MRD
External Port
,
DIS_DDR2CTL
DDR2PADCTL1
3-69
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