Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 718

Clocking
Transmit Buffer Control Register (UARTxTXCTL). Controls core or
DMA operation.
Receive Buffer Control Register (UARTxRXCTL). Controls core or
DMA operation.
Interrupt Enable Control Register (UARTxIER). Enables interrupt
requests from system handling.
Line Status Register (UARTxLSR). Returns status of controls format of
the data character frames as overrun or framing errors and break
interrupts.
Transmit Status Register (UARTxTXSTAT). Returns status of core or
DMA operation.
Receive Status Register (UARTxRXSTAT). Returns status of core or
DMA operation.
Interrupt Identification Status Register (UARTxIIR). Provides status of
all interrupts and combines them into one channel.
Clocking
The fundamental timing clock of the UART module is peripheral
clock/16 ( /16).
PCLK
The bit rate is characterized by the peripheral clock (
divisor. The divisor is split into the UART divisor latch low byte register
( ) and the UART divisor latch high byte register (
UARTDLL
registers form a 16-bit divisor. The baud clock is divided by 16 so that:
• Divisor = 1 when
• Divisor = 65,535 when
20-4
www.BDTIC.com/ADI
= 1
UARTDLL UARTDLH
=
UARTDLL
ADSP-214xx SHARC Processor Hardware Reference
) and the 16-bit
PCLK
UARTDLH
= 0
= FF
UARTDLH
). These