Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 629

Transfer Initiate Mode
When the processor is enabled as a master, the initiation of a transfer is
defined by the
TIMOD
the interface, a new transfer is started upon either a read of the
isters or a write to the
Table 15-6. Transfer Initiation
TIMOD Function
00 Core Receive
and Transmit
01 Core Transmit
and Receive
10 Transmit or
Receive with
DMA
11 Reserved
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Serial Peripheral Interface Ports
bits (1–0). Based on these two bits and the status of
registers. This is summarized in
TXSPIx
Transfer Initiated Upon
Initiate new single word transfer
upon read of RXSPI and previous
transfer completed. The SPICLK
is generated after the data is read
from the buffer. In this configura-
tion, a dummy read is needed ini-
tially to receive all the data
transmitted from the transmitter.
Initiate new single word transfer
upon write to TXSPI and previous
transfer completed.
Initiate new multiword transfer
upon write to DMA enable bit.
Individual word transfers begin
with either a DMA write to TXSPI
or a DMA read of RXSPI depend-
ing on the direction of the transfer
as specified by the SPIRCV bit.
RXSPIx
Table
Action, Interrupt
The SPI interrupt is latched in every core
clock cycle in which the RXSPI buffer
has a word in it.
Emptying the RXSPI buffer or disabling
the SPI port at the same time (SPIEN =
0) stops the interrupt latch.
The SPI interrupt is latched in every core
clock cycle in which the TXSPI buffer is
empty.
Writing to the TXSPI buffer or disabling
the SPI port at the same time (SPIEN =
0) stops the interrupt latch.
If chaining is disabled, the SPI interrupt
is latched in the cycle when the DMA
count decrements from 1 to 0.
If chaining is enabled, interrupt function
is based on the PCI bit in the CP register.
If PCI = 0, the SPI interrupt is latched at
the end of the DMA sequence. If PCI =
1, then the SPI interrupt is latched after
each DMA in the sequence.
reg-
15-6.
15-13