Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 847

Table A-8. EPCTL Register Bit Descriptions (RW) (Cont'd)
Bit Name
21–19 FRZSP
31–19 Reserved
1 The EPCTL register automatically reads the DDR2CTL0 page size setting (DDR2CAW), pro-
grams just need to program the EPCTL for selecting page size freeze mode.
AMI Control Registers (AMICTLx)
The
AMICTL0–3
of external memory. These registers are shown in
described in Table
cycles are derived from the DDR2 clock.
31 30
PREDIS
Disable Predictive Reads
RHC (20–18)
Read Hold Cycle
15
IC (16–14)
HC (13–11
Bus Hold Cycle (at end of write access)
WS (10–6)
Wait States
ACKEN
ACK Pin Enable
Figure A-7. AMICTLx Registers
ADSP-214xx SHARC Processor Hardware Reference
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Description
Arbitration Freezing Length for SPORT DMA.
000 = No Freezing
001 = 4 Accesses
010 = 8 Accesses
011 = 16 Accesses
100 = 32 Accesses
101 = Page size of DDR2
110, 111 = Reserved
registers control the mode of operations for the four banks
A-9. Note for all AMI timing bit settings, all defined
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Registers Reference
1
Figure A-7
21 20 19 18 17 16
IC
Bus Idle Cycle
FLSH
AMI Buffer Flush
6 5 4 3 2 1 0
AMIEN
AMI Enable
PKDIS
Packing/Unpacking Disable
MSWF
Most Significant Word First
and
A-21