Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 927

Control Base Address Register (MLB_CBCR)
The register, described in
MLB_CBCR
the system memory buffers of all control channels in the device.
Table A-64. MLB_CBCR Register Bit Descriptions (RW)
Bit Name
4–0 CTBA
15–5 Reserved
20–16 CRBA
31–21 Reserved
Isynchronous Base Address Register (MLB_IBCR)
The register, described in
MLB_IBCR
the system memory buffers of all isynchronous channels in the device.
Table A-65. MLB_ABCR Register Bit Descriptions (RW)
Bit Name
4–0 ATBA
15–5 Reserved
20–16 ARBA
31–21 Reserved
Logical Channel Registers
The MLB controller supports up to 31 logical channels. Therefore the
variable in the register names is valid for x = 0–30. This section lists all
different control and status registers related to the logical channels.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Table A-64, hold the base address of
Description
Control transmit base address for DMA mode
Control receive base address for DMA mode
Table A-65, holds the base address of
Description
Isynchronous transmit base address for DMA mode
Isynchronous receive base address for DMA mode
Registers Reference
A-101