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• On countdown from a programmable value
• Daily at a specific time
• On a specific day and time
• On a 1 Hz clock failure
• Completion on pending writes to any 1 Hz registers
Service Interrupts
In the service routine the
cause of the interrupt. While reading the status registerthe RTC automat-
ically clears the respective status bit ensuring that the cause has been
cleared before ending the routine.
The RTC can be programmed to provide an interrupt at the completion
of all pending writes to any of the 1 Hz registers (
). Interrupts can be individually enabled or disabled using the
RTC_INIT
RTC interrupt control register (
mined by reading the RTC interrupt status register (
The RTC interrupt is set whenever an event latched into the
register is enabled in the
cleared whenever all enabled and set bits in
bits in
RTC_CTL
Debug Features
The following section provides information on debugging features avail-
able with the watchdog timer.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
RTC_STAT
RTC_INIT
register. The pending RTC interrupt is
RTC_CTL
corresponding to pending events are cleared.
Real-Time Clock—ADSP-2147x
register should be read to identify the
RTC_CLOCK
). Interrupt status can be deter-
RTC_STAT
are read, or when all
RTC_STAT
, and
).
RTC_STAT
18-11
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