Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 701

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To ensure that writes between the core voltage and RTC voltage

domain are properly synchronized, all write commands should be

issued immediately after a seconds' event in the

This two step sequence results in a write latency of up to 1 second. While

the write sequence is ongoing, the write pending (

Resetting or powering down the peripherals while a write is in progress,

(that is when this bit is set) is forbidden. Subsequent writes to the same

Do not attempt write to the

registers when the RTC oscillator is powered down or when the

During initialization, after a write of the

sure that the

other registers.

Power-Up, Power-Down and Reset

The inclusion of the power-down bit (

that the RTC may not be used in certain applications introduces specific

constraints on the power-up and reset behavior of the RTC. These are

described below.

1. When the RTC is powered-up for the first time, it remains in an

undefined state until the core powers-up and the corresponding

power-down bit in the

Programs should clear

set if it is not.

2. After clearing the

until the first seconds' event before it writes the timer and alarm

registers. This is because the oscillator takes a TSTARTUP time

before the clock gets generated.

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

Real-Time Clock—ADSP-2147x

bit is cleared before attempting writes to

if the RTC function is desired and

bit the application has to wait at least

) as well as the possibility

) bit is set in the

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