Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 633

Variable Frame Delay for Slave
When the processor is configured as an SPI slave, the SPI master must
drive an
SPICLK
parameters, please refer to the appropriate product data sheet.
As shown in Figure
(T2), and the sequential transfer delay time (T3) must always be greater
than or equal to one-half the
successive word transfers (T4) is two
measured from the last active edge of
edge of
SPICLK
configuration of the SPI (
This is shown as:
T4 = 1.5 SPI clock period + T3
and
T3 = 0.5 SPICLK period for STDC = 0.
×
T3 = STDC SPICLK period for STDC > 0.

Unlike previous SHARC processors, a variable frame delay is
included to increase SPI timing flexability.
For a master device with
the register), this means that the slave-select output is inactive
SPCTL
(high) for at least one-half the
each always be equal to one-half the
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
signal that conforms with
15-7, the
SPIDS
SPICLK
of the next word. This calculation is independent from the
,
CPHASE SPIMS
= 0 or
CPHASE
SPICLK
Serial Peripheral Interface Ports
Figure 15-7. For exact timing
lead time (T1), the
period. The minimum time between
periods. This time period is
SPICLK
of one word to the first active
SPICLK
, and so on).
= 1 (with
CPHASE
period. In this case, T1 and T2 are
period.
SPICLK
lag time
SPIDS
set to 1 in
AUTODS
15-17