Self-Refresh Mode - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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SDRAM Controller (ADSP-2147x/ADSP-2148x)

Self-Refresh Mode

This mode causes refresh operations to be performed internally by the

SDRAM, without any external control. This means that the SDC does not

generate any auto-refresh cycles while the SDRAM is in self-refresh mode.

Self-refresh entry—Self-refresh mode is enabled by writing a 1 to the

bit of the SDRAM memory control register (

pin and puts the SDRAM in self-refresh mode if no access is

currently underway. The SDRAM remains in self-refresh mode for at least

and until an internal access (read/write) to SDRAM space occurs.

Self-refresh exit—When any SDRAM access occurs, the SDC asserts

high which causes the SDRAM to exit from self-refresh mode. The

SDC waits to meet the t

issues an auto-refresh command. After the auto-refresh command, the

SDC waits for the t

executing the activate command for the transfer that caused the SDRAM

to exit self-refresh mode. Therefore, the latency from when a transfer is

received by the SDC while in self-refresh mode, until the activate com-

mand occurs for that transfer, is 2 × (t

System clock during self-refresh mode. Note that the

abled by the SDC during self-refresh mode. However, software may

disable the clocks by clearing the

grams should ensure that all applicable clock timing specifications are met

before the transfer to SDRAM address space (which causes the controller

to exit the self-refresh mode). If a transfer occurs to SDRAM address space

access does not occur externally, leaving the SDRAM in self-refresh mode.

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specification (t

specification (t

bit is cleared, an internal bus error is generated, and the

ADSP-214xx SHARC Processor Hardware Reference

) to be met before

). This deasserts

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