Delay Line Dma - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

TAP LIST POINTER (TPEP)
DESTINATION
INDEX (IIEP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DESTINATION BUFFER
Figure 3-27. Circular Gather DMA (Reads)

Delay Line DMA

Delay line DMA is used to support reads and writes to external delay line
buffers with limited core interaction. In this sense, delay line DMA is basi-
cally a quantity of integrated writes followed by reads from external
memory-called a delay line DMA access. Delay line DMA is described in
the following sections.
The delay line DMA access consists of the following accesses in the order
listed and is shown in
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
TAP LIST BUFFER
4
12
20
28
36
SOURCE INDEX (EIEP)
SOURCE BASE (EBEP)
Figure 3-28 on page
External Port
EIEP + 20
9
10
11
12
1
EIEP + 4
2
3
4
13
EIEP + 28
14
15
16
5
EIEP + 12
6
7
8
EIEP + 36
17
18
19
20
SOURCE BUFFER
3-113. Note that in the figure
3-111