Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 237

External Port
the internal count register ( ), and is the same for every tap. The
ICEPx
read/write pointer in external index register ( ) serves as the index
EIEPx
address for these read/writes.
TL[N] is the first tap list entry in the internal memory as pointed by the
, the tap list pointer. The tap list entries are 27-bit signed integers.
TPEP
Therefore, for each read/write block, the DMA state machine fetches the
offset from the tap list. The offset is added to the value to get the
EIEP
start address of the next block. The external addresses are circular buffered
if circular buffering is enabled (Figure 3-26, Figure 3-27).
Once the register for the final tap decrements to zero (both and
ICEP TCEP
are zero), then the tap list DMA access is complete and the DMA
ICEP
completion interrupt is generated (if chaining is enabled the interrupt
depends on the bit setting).
PCI
The write back mode ( bit) is not applicable for tap list based DMA
WRBEN
(as the addressing is pre-modify, and therefore the value coincides
EIEP
with the TCB value even at the end of DMA). So even if the bit is
WRBEN
set in tap list DMA mode, the write backs do not occur.
ADSP-214xx SHARC Processor Hardware Reference 3-107
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