Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 638

Data Transfers
When enabled as a master, the DMA engine transmits or receives data as
follows:
• If the SPI system is configured for transmitting, the DMA engine
reads data from memory into the DMA FIFO. Data from the
DMA FIFO is loaded into the
transmit shift register. This initiates the transfer on the SPI port.
• If configured to receive, data from the
cally loaded into the DMA FIFO. Then the DMA engine reads
data from the DMA FIFO and writes to memory. Finally, the SPI
initiates the receive transfer. The SPI generates the programmed
signal pulses on
from
MISO
words until the SPI DMA word count register transitions from 1 to
0.

Do not write to the
DMA operation because DMA data will be overwritten. Similarly,
do not read from the
operations. DMA Interrupts are generated based on DMA events
and are configured in the SPIDMACx registers. In order for a
transmit DMA operation to begin, the transmit buffer (
must initially be empty (
this means that the
pose other than SPI transfers. Writing to the
software sets the

For receive master DMA the
buffer and DMA FIFO are full (even if the DMA count is already
zero). Therefore,
filling junk data in the
must be flushed before a new DMA is initiated.
15-22
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and the data is shifted out of
SPICLK
simultaneously. The SPI continues sending or receiving
buffer during an active SPI transmit
TXSPIx
buffer during active SPI DMA receive
RXSPIx
= 0). While this is normally the case,
TXS
buffer should not be used for any pur-
TXSPIx
bit.
TXS
runs for an additional five word transfers
SPICLK
RXSPIx
ADSP-214xx SHARC Processor Hardware Reference
buffer and then into the
TXSPIx
buffer is automati-
RXSPIx
TXSPIx
stops only when the
SPICLK
buffer and DMA FIFO. The FIFOs
and in
MOSI
)
TXSPIx
buffer via the
RXSPI