Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 506

Data Transfers
Moreover, transmitting or receiving words smaller than five bits
may cause incorrect operation when all the DMA channels are
enabled with no DMA chaining.
DMA Chain Insertion Mode
It is possible to insert a single SPORT DMA operation or another DMA
chain within an active SPORT DMA chain. Programs may need to per-
form insertion when a high priority DMA requires service and cannot wait
for the current chain to finish.
When DMA on a channel is disabled and chaining on the channel is
enabled, the DMA channel is in chain insertion mode. This mode allows a
program to insert a new DMA or DMA chain within the current chain
without effecting the current DMA transfer.
Chain insertion mode operates the same as non-chained DMA mode.
When the current DMA transfer ends, an interrupt request occurs and no
TCBs are loaded. This interrupt request is independent of the
state.
Chain insertion should not be set up as an initial mode of operation. This
mode should only be used to insert one or more TCBs into an active
DMA chaining sequence. For more information, see
Insertion Mode" on page
Frame Sync Generation
The frame syncs are generated if the transmit or receive buffers are
updated according to the DIFS bit setting (=0). The SPORT DMA con-
troller ensure that the data buffers are updated accordingly.
If both A and B channels are enabled, one of the following can occur.
10-48
www.BDTIC.com/ADI
10-56.
ADSP-214xx SHARC Processor Hardware Reference
bit
PCI
"Enter DMA Chain