Page 1 ® ADSP-2106x SHARC Processor User’s Manual Revision 2.1, March 2004 Part Number 82-000795-03 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 www.BDTIC.com/ADI...
Page 2 Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use;...
Page 3: Table Of Contents
Contents CHAPTER 1 INTRODUCTION OVERVIEW ......................1-1 ADSP-21000 FAMILY FEATURES & BENEFITS ..........1-5 1.2.1 System-Level Enhancements ................1-6 1.2.2 Why Floating-Point DSP? ................1-7 ADSP-2106X ARCHITECTURE ................1-8 1.3.1 Core Processor ....................1-8 1.3.1.1 Computation Units ..................1-8 1.3.1.2 Data Register File ..................1-8 1.3.1.3 Program Sequencer & Data Address Generators ........1-9 1.3.1.4 Instruction Cache ..................1-10 1.3.1.5...
Page 4 Contents ALU ........................2-5 2.5.1 ALU Operation ....................2-6 2.5.2 ALU Operating Modes ..................2-6 2.5.2.1 Saturation Mode ..................2-7 2.5.2.2 Floating-Point Rounding Modes ..............2-7 2.5.2.3 Floating-Point Rounding Boundary..............2-7 2.5.3 ALU Status Flags .....................2-7 2.5.3.1 ALU Zero Flag (AZ) ..................2-8 2.5.3.2 ALU Underflow Flag (AZ, AUS) ..............2-8 2.5.3.3 ALU Negative Flag (AN) ................2-8 2.5.3.4...
Page 5 Contents MULTIFUNCTION COMPUTATIONS ..............2-26 REGISTER FILE ....................2-27 2.9.1 Alternate (Secondary) Registers ..............2-28 CHAPTER 3 PROGRAM SEQUENCING OVERVIEW ......................3-1 3.1.1 Instruction Cycle ....................3-2 3.1.2 Program Sequencer Architecture ..............3-3 3.1.2.1 Program Sequencer Registers & System Registers ........3-5 PROGRAM SEQUENCER OPERATIONS ............3-6 3.2.1 Sequential Instruction Flow ................3-6 3.2.2 Program Memory Data Accesses ..............3-6...
Page 6 Contents 3.6.9.1 Asynchronous External Interrupts .............3-32 3.6.10 Multiprocessor Vector Interrupts (VIRPT) ............3-32 TIMER ........................3-33 3.7.1 Timer Enable/Disable..................3-34 3.7.2 Timer Interrupts....................3-35 3.7.3 Timer Registers....................3-36 STACK FLAGS....................3-36 IDLE & IDLE16 ....................3-37 3.10 INSTRUCTION CACHE ..................3-38 3.10.1 Cache Architecture ..................3-38 3.10.2 Cache Efficiency ....................3-39 3.10.3 Cache Disable &...
Page 7 Contents ADSP-2106X MEMORY MAP ................5-9 5.2.1 ADSP-21060 Internal Memory Space ............5-11 5.2.2 ADSP-21062 Internal Memory Space ............5-14 5.2.3 ADSP-21061 Internal Memory Space ............5-16 5.2.4 Porting Code from ADSP-21060 to ADSP-21062 or ADSP-21061 ....5-18 5.2.5 Multiprocessor Memory Space ..............5-18 5.2.6 External Memory Space .................5-19 5.2.7 Memory Space Access Restrictions ..............5-19 INTERNAL MEMORY ORGANIZATION &...
Page 8 Contents 6.2.1 External Port DMA Control Registers ..............6-9 6.2.2 Serial Port DMA Control.................6-14 6.2.3 Link Port DMA Control ...................6-15 6.2.4 Port Selection For Shared DMA Channels ............6-17 6.2.5 DMA Channel Status Register (DMASTAT) ..........6-18 DMA CONTROLLER OPERATION..............6-20 6.3.1 DMA Channel Parameter Registers...............6-21 6.3.2 Internal Request &...
Page 9 Contents 7.2.2.1 Link Port Data Transfers In A Cluster ............7-7 7.2.3 SIMD Multiprocessing ..................7-8 MULTIPROCESSOR BUS ARBITRATION ............7-9 7.3.1 Bus Arbitration Protocol .................7-10 7.3.2 Bus Arbitration Priority (RPBA) ..............7-14 7.3.3 Bus Mastership Timeout ................7-15 7.3.4 Core Priority Access ..................7-16 7.3.5 Bus Synchronization After Reset ..............7-19 SLAVE DIRECT READS &...
Page 10 Contents 8.3.4 Shadow Write FIFO ..................8-17 DATA TRANSFERS THROUGH THE EPBX BUFFERS ........8-18 8.4.1 Single-Word Transfers ...................8-18 8.4.1.1 Interrupts For Single-Word Transfers ............8-19 8.4.2 DMA Transfers ....................8-20 8.4.2.1 DMA Transfers To Internal Memory ............8-20 8.4.2.2 DMA Transfers To External Memory ............8-21 DATA PACKING....................8-21 8.5.1 Packing Control Bits In SYSCON ..............8-21...
Page 11 Contents 9.5.1 DMA Chaining For Link Ports ................9-18 LINK PORT INTERRUPTS ................9-18 9.6.1 Link Port Interrupts With DMA Disabled ............9-18 9.6.2 Link Port Interrupts With DMA Enabled ............9-19 9.6.3 Link Port Service Request Interrupts (LSRQ) ..........9-19 TRANSMISSION ERROR DETECTION ............9-23 TOKEN PASSING ....................9-23 LINK TRANSMISSION LINES ................9-26 9.10...
Page 12 Contents 10.7.1 Frame Syncs In Multichannel Mode.............10-26 10.7.2 Multichannel Control Bits In STCTL, SRCTL ..........10-27 10.7.2.1 Multichannel Enable ................10-27 10.7.2.2 Number Of Channels ................10-27 10.7.2.3 Current Channel Indicator ...............10-27 10.7.2.4 Multichannel Frame Delay ...............10-28 10.7.3 Channel Selection Registers ................10-28 10.7.4 SPORT Receive Comparison Registers ............10-29 10.8 TRANSFERRING DATA BETWEEN SPORTS AND MEMORY ......10-31...
Page 13 Contents 11.5.1 Clock Specifications & Jitter.................11-19 11.5.2 Clock Distribution ..................11-19 11.5.3 Point-To-Point Connections .................11-21 11.5.4 Signal Integrity .....................11-22 11.5.5 Other Recommendations & Suggestions .............11-24 11.5.6 Decoupling Capacitors & Ground Planes ............11-25 11.5.7 Oscilloscope Probes ..................11-26 11.5.8 Recommended Reading ................11-26 11.6 BOOTING ......................11-27 11.6.1 Selecting The Booting Mode ................11-27...
Page 14 Contents APPENDIX A INSTRUCTION SET REFERENCE OVERVIEW......................A-1 INSTRUCTION SET SUMMARY .................A-2 OPCODE NOTATION ..................A-8 UNIVERSAL REGISTER CODES ..............A-12 GROUP I. COMPUTE AND MOVE INSTRUCTIONS ........A-15 Compute / dreg÷DM / dreg÷PM ..............A-16 Compute ......................A-17 Compute / ureg÷DM|PM , register modify .............A-18 Compute / dreg÷DM|PM , immediate modify ..........A-20 Compute / ureg÷ureg ..................A-22 Immediate shift / dreg÷DM|PM..............A-24...
Page 15 Contents APPENDIX B COMPUTE OPERATION REFERENCE OVERVIEW ......................B–1 SINGLE-FUNCTION OPERATIONS..............B–1 B.2.1 ALU Operations ....................B–2 Rn = Rx + Ry ....................B–4 Rn = Rx – Ry ....................B–5 Rn = Rx + Ry + CI ..................B–6 Rn = Rx – Ry + CI – 1 ................B–7 Rn = (Rx + Ry)/2 ..................B–8 COMP(Rx, Ry) ...................B–9 Rn = Rx + CI .....................B–10...
Page 16 Contents Rn = TRUNC Fx BY Ry / Rn = TRUNC Fx..........B–37 Fn = FLOAT Rx BY Ry / Fn = FLOAT Rx..........B–38 Fn = RECIPS Fx ..................B–39 Fn = RSQRTS Fx ..................B–40 Fn = Fx COPYSIGN Fy ................B–41 Fn = MIN(Fx, Fy) ..................B–42 Fn = MAX(Fx, Fy) ..................B–43 Fn = CLIP Fx BY Fy .................B–44 B.2.2...
Page 17 Contents MULTIFUNCTION COMPUTATIONS ...............B–76 Dual Add/Subtract (Fixed-Pt.)..............B–77 Dual Add/Subtract (Floating-Pt) ...............B–78 Parallel Multiplier & ALU (Fixed-Pt.) ............B–79 Parallel Multiplier & ALU (Floating-Pt.) .............B–80 Parallel Multiplier & Dual Add/Subtract.............B–82 APPENDIX C NUMERIC FORMATS OVERVIEW ......................C-1 IEEE SINGLE-PRECISION FLOATING-POINT DATA FORMAT .......C-1 EXTENDED PRECISION FLOATING-POINT FORMAT ........C-2 SHORT WORD FLOATING-POINT FORMAT ............C-3 FIXED-POINT FORMATS ...................C-5...
Page 18 SHARC GLOSSARY APPENDIX H DOCUMENTATION ERRATA INDEX FIGURES Figure 1.1 Super Harvard Architecture ..............1-2 Figure 1.2 ADSP-2106x SHARC Block Diagram .............1-3 Figure 1.3 ADSP-2106x System ................1-4 Figure 1.4 System Design and Development Process ...........1-17 Figure 2.1 Computation Units ...................2-2 Figure 2.2 Multiplier Fixed-Point Result Placement ..........2-12...
Page 19 Contents Figure 2.4 Register File Fields For Shifter Instructions ..........2-20 Figure 2.5 Register File Fields For FDEP, FEXT Instructions ........2-20 Figure 2.6 Bit Field Deposit Instruction ..............2-21 Figure 2.7 Bit Field Deposit Example ..............2-22 Figure 2.8 Bit Field Extract Example ..............2-23 Figure 2.9 Input Registers For Multifunction Computations (ALU &...
Page 20 Contents Figure 5.11 Short Word Addresses ................5-28 Figure 5.12 Preprocessing of 16-Bit Short Word Addresses........5-29 Figure 5.13 48-Bit Words & 32-Bit Words Mixed In A Memory Block (ADSP-21060) ..................5-31 Figure 5.14 48-Bit Words & 32-Bit Words Mixed In A Memory Block (ADSP-21062 or ADSP-21061).............5-32 Figure 5.a External Port Data Alignment ..............5-35...
Page 21 Contents Figure 8.6 SYSTAT Register ..................8-30 Figure 8.7 Basic System Bus Interface ..............8-35 Figure 8.8 Bidirectional System Bus Interface............8-37 Figure 8.9 ADSP-2106x Subsystems On A System Bus ........8-41 Figure 9.a Link Port Pin Connections ...............9-2 Figure 9.b Link Port Communication Examples ............9-3 Figure 9.1 Link Ports &...
Page 22 Contents Figure 11.12 Multiple SHARCs Booting From One EPROM, Processors-Take-Turns ...............11-36 Figure 11.13 Multiple SHARCs Booting From One EPROM, One-Boots-Others ................11-36 Figure A.1 Map 1 Universal Register Codes ............A-12 Figure A.2 Map 2 Universal Rgister Codes ............A-13 Figure B.1 Allowed Input Registers For Multifunction Computations .....B-76 Figure C.1 IEEE 32-Bit Single-Precision Floating-Point Format ......C-1 Figure C.2...
Page 23 Contents Table 6.5 STCTLx/SRCTLx Control Bits For Serial Port DMA ......6-14 Table 6.6 SPORT DMA Interrupts .................6-15 Table 6.7 Link Port DMA Channels ...............6-15 Table 6.8 LCTL Control Bits For Link Port DMA ...........6-16 Table 6.9 Link Buffer DMA Interrupts ..............6-17 Table 6.10 DMASTAT Register ................6-19 Table 6.11...
Page 24 Contents Table 11.3 DMA Channel 6 Parameter Register Initialization For EPROM Booting ................11-30 Table 11.4 Ext. Port DMA Channel 6 Parameter Register Initialization For Host Booting .................11-33 Table 11.5 Data Delays & Throughputs ..............11-46 Table 11.6 Latencies & Throughputs ..............11-47 Table B.1 Fixed-Point ALU Operations ..............B-2 Table B.2...
Page 25: Chapter 1 Introduction
I/O, plus crossbar switch memory connections, comprise the Super Harvard Architecture of the ADSP-2106x. The ADSP-2106x SHARC represents a new standard of integration for digital signal processors, combining a high-performance floating-point DSP core with integrated, on-chip features including a host processor interface, DMA controller, serial ports, and link port and shared bus connectivity for glueless DSP multiprocessing.
Page 26: Figure 1.1 Super Harvard Architecture
1 Introduction Figure 1.2 also shows the three on-chip buses of the ADSP-2106x: the PM bus (program memory), DM bus (data memory), and I/O bus. The PM bus is used to access either instructions or data. During a single cycle the processor can access two data operands, one over the PM bus and one over the DM bus, an instruction (from the cache), and perform a DMA transfer.
Page 27: Figure 1.2 Adsp-2106X Sharc Block Diagram
LINK PORTS I/O Processor * not available on the ADSP-21061 Figure 1.2 ADSP-2106x SHARC Block Diagram This user’s manual contains architectural information and an instruction set description required for the design and programming of ADSP-2106x-based systems. In addition to this manual, hardware...
Page 28: Figure 1.3 Adsp-2106X System
1 Introduction This manual covers three ADSP-2106x processors: the ADSP-21060, ADSP-21062, and ADSP-21061. The ADSP-21060 contains 4 megabits of on- chip SRAM, the ADSP-21062 contains 2 megabits, and the ADSP-21061 contains 1 megabit. The Memory chapter of this manual describes the differences in memory architecture and programming considerations of the three processors.
Page 29: Adsp-21000 Family Features & Benefits
Introduction ADSP-21000 FAMILY FEATURES & BENEFITS The ADSP-2106x SHARC processors belong to the ADSP-21000 Family of floating-point digital signal processors (DSPs). The ADSP-21000 Family architecture further addresses the five central requirements for DSPs established in the ADSP-2100 Family of 16-bit fixed-point DSPs: •...
Page 30: System-Level Enhancements
1 Introduction Dual Address Generators. The ADSP-21000 Family processors have two data address generators (DAGs) that provide immediate or indirect (pre- and post-modify) addressing. Modulus and bit-reverse operations are supported with no constraints on data buffer placement. Efficient Program Sequencing. In addition to zero-overhead loops, the ADSP-21000 Family processors support single-cycle setup and exit for loops.
Page 31: Why Floating-Point Dsp
Introduction IEEE Formats. The ADSP-21000 Family processors support IEEE floating-point data formats. This means that algorithms developed on IEEE-compatible processors and workstations are portable across processors without concern for possible instability introduced by biased rounding or inconsistent error handling. 1.2.2 Why Floating-Point DSP? A digital signal processor’s data format determines its ability to handle signals of differing precision, dynamic range, and signal-to-noise...
Page 32: Adsp-2106X Architecture
1 Introduction ADSP-2106X ARCHITECTURE The following sections summarize the features of the ADSP-2106x SHARC architecture. These features are described in greater detail in succeeding chapters. 1.3.1 Core Processor The core processor of the ADSP-2106x consists of three computation units, a program sequencer, two data address generators, timer, instruction cache, and data register file.
Page 33: Program Sequencer & Data Address Generators
Introduction 1.3.1.3 Program Sequencer & Data Address Generators Two dedicated address generators and a program sequencer supply addresses for memory accesses. Together the sequencer and data address generators allow computational operations to execute with maximum efficiency since the computation units can be devoted exclusively to processing data.
Page 34: Instruction Cache
1 Introduction 1.3.1.4 Instruction Cache The program sequencer includes a 32-word instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only instructions whose fetches conflict with program memory data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and FFT butterfly processing.
Page 35: Internal Data Transfers
Introduction The PM Address bus and DM Address bus are used to transfer the addresses for instructions and data. The PM Data bus and DM Data bus are used to transfer the data or instructions stored in each type of memory.
Page 36: Instruction Set
1 Introduction 1.3.1.10 Instruction Set The ADSP-21000 Family instruction set provides a wide variety of programming capabilities. Multifunction instructions enable computations in parallel with data transfers, as well as simultaneous multiplier and ALU operations. The addressing power of the ADSP-2106x gives you flexibility in moving data both internally and externally.
Page 37: External Memory & Peripherals Interface
Introduction While each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the DM bus for transfers, and the other block stores instructions and data, using the PM bus for transfers. Using the DM bus and PM bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers.
Page 38: Multiprocessing
1 Introduction 1.3.5 Multiprocessing The ADSP-2106x offers powerful features tailored to multiprocessing DSP systems. The unified address space allows direct interprocessor accesses of each ADSP-2106x’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six ADSP-2106xs and a host processor. Master processor changeover incurs only one cycle of overhead.
Page 39: Link Ports
Introduction 1.3.6.2 Link Ports The ADSP-21062 and ADSP-21060 feature six 4-bit link ports that provide additional I/O capabilities. The link ports can be clocked twice per cycle, allowing each to transfer 8 bits per cycle. Link port I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems.
Page 40: Booting
1 Introduction The ten DMA channels of the ADSP-21060 and ADSP-21062 are numbered as shown below: Data Channel# Buffer Description DMA Channel 0 Serial Port 0 Receive DMA Channel 1 RX1 (or LBUF0) Serial Port 1 Receive (or Link Buffer 0) DMA Channel 2 Serial Port 0 Transmit DMA Channel 3...
Page 41: Figure 1.4 System Design And Development Process
Introduction Numerical C provides extensions to the C language for array selection, vector math operations, complex data types, circular pointers, and variably-dimensioned arrays. Other components of the development software include a C Runtime Library with custom DSP functions, C and assembly language Debugger, Assembler, Assembly Library/ Librarian, Linker, and Simulator.
Page 42: Mesh Multiprocessing
Further details and ordering information are available in the ADSP-21000 Family Hardware & Software Development Tools data sheet. This data sheet can be requested from any Analog Devices sales office or distributor. MESH MULTIPROCESSING Mesh multiprocessing is a parallel processing system architecture that offers high throughput, system flexibility, and software simplicity.
Page 43: Computation Units
Computation Units OVERVIEW The computation units of the ADSP-2106x provide the numeric processing power for performing DSP algorithms. The ADSP-2106x contains three computation units: an arithmetic/logic unit (ALU), a multiplier and a shifter. Both fixed-point and floating-point operations are supported by the processor.
Page 44: Ieee Floating-Point Operations
2 Computation Units PM Data Bus DM Data Bus REGISTER FILE MULTIPLIER SHIFTER 16 x 40-bit Figure 2.1 Computation Units This chapter covers the following topics: • Data Formats and Rounding • ALU Architecture and Functions • Multiplier Architecture and Functions •...
Page 45: Extended Floating-Point Precision
Computation Units • Denormal operands are flushed to zero when input to a computation unit and do not generate an underflow exception. Any denormal or underflow result from an arithmetic operation is flushed to zero and an underflow exception is generated. •...
Page 46: Floating-Point Exceptions
2 Computation Units 2.2.3 Floating-Point Exceptions The multiplier and ALU each provide exception information when executing floating-point operations. Each unit updates overflow, underflow and invalid operation flags in the arithmetic status (ASTAT) register and in the sticky status (STKY) register. An underflow, overflow or invalid operation from any unit also generates a maskable interrupt.
Page 47: Alu
Computation Units Round-Toward-Nearest. If the result before rounding is not exactly representable in the destination format, the rounded result is that number which is nearer to the result before rounding. If the result before rounding is exactly halfway between two numbers in the destination format (differing by an LSB), the rounded result is that number which has an LSB equal to zero.
Page 48: Alu Operation
2 Computation Units 2.5.1 ALU Operation The ALU takes one or two input operands, called the X input and the Y input, which can be any data registers in the register file. It usually returns one result; in add/subtract operations it returns two results, and in compare operations it returns no result (only flags are updated).
Page 49: Saturation Mode
Computation Units 2.5.2.1 Saturation Mode In saturation mode, all positive fixed-point overflows cause the maximum positive fixed-point number (0x7FFF FFFF) to be returned, and all negative overflows cause the maximum negative number (0x8000 0000) to be returned. If the ALUSAT bit is set, fixed-point results that overflow are saturated.
Page 50: Alu Zero Flag (Az)
2 Computation Units STKY Name Definition ALU floating-point underflow ALU floating-point overflow ALU fixed-point overflow ALU floating-point invalid operation Flag update occurs at the end of the cycle in which the status is generated and is available on the next cycle. If a program writes the ASTAT register or STKY register explicitly in the same cycle that the ALU is performing an operation, the explicit write to ASTAT or STKY supersedes any flag update from the ALU operation.
Page 51: Alu Fixed-Point Carry Flag (Ac)
Computation Units 2.5.3.5 ALU Fixed-Point Carry Flag (AC) The carry flag is determined for all fixed-point ALU operations. For fixed-point arithmetic operations, AC is set if there is a carry out of most significant bit of the result, and is otherwise cleared. AC is cleared for fixed-point logic, PASS, MIN, MAX, COMP, ABS, and CLIP operations.
Page 52: Alu Instruction Summary
2 Computation Units 2.5.4 ALU Instruction Summary Instruction ASTAT Status Flags STKY Status Flags Fixed-point: AZ AV AN AC AF CACC AUS AVS AOS AIS Rn = Rx + Ry – – – – Rn = Rx – Ry – –...
Page 53: Multiplier
Computation Units MULTIPLIER The multiplier performs fixed-point or floating-point multiplication and fixed- point multiply/accumulate operations. Fixed-point multiply/accumulates may be performed with either cumulative addition or cumulative subtraction. Floating-point multiply/accumulates can be accomplished through parallel operation of the ALU and multiplier, using multifunction instructions. See “Multifunction Computations”...
Page 54: Fixed-Point Results
2 Computation Units 2.6.2 Fixed-Point Results Fixed-point operations yield 80-bit results in the MR register. The location of a result in the 80-bit field depends on whether the result is in fractional or integer format, as shown in Figure 2.2. If the result is sent directly to the register file, the 32 bits that have the same format as the input data are transferred, i.e.
Page 55: Fixed-Point Operations
Computation Units 16 bits 16 bits 8 bits SIGN EXTEND ZEROS 32 bits 8 bits ZEROS 32 bits 8 bits ZEROS Figure 2.3 MR Transfer Formats may specify either result register for accumulation, regardless of the state of the SRCU bit. Thus, instead of using the MR registers as a primary and an alternate, you can use them as two parallel accumulators.
Page 56: Round Mr Register
2 Computation Units 2.6.3.2 Round MR Register Rounding of a fixed-point result occurs either as part of a multiply or multiply/accumulate operation or as an explicit operation on the MR register. The rounding operation applies only to fractional results (integer results are not affected) and rounds the 80-bit MR value to nearest at bit 32, i.e.
Page 57: Floating-Point Operating Modes
Computation Units 2.6.4 Floating-Point Operating Modes The multiplier is affected by two mode status bits in the MODE1 register: the rounding mode and rounding boundary bits, which affect operations in both the multiplier and the ALU. MODE1 Name Function TRUNC 1=Truncation;...
Page 58: Multiplier Underflow Flag (Mu)
2 Computation Units STKY Name Definition Multiplier fixed-point overflow Multiplier floating-point overflow Multiplier underflow Multiplier floating-point invalid operation Flag update occurs at the end of the cycle in which the status is generated and is available on the next cycle. If a program writes the ASTAT register or STKY register explicitly in the same cycle that the multiplier is performing an operation, the explicit write to ASTAT or STKY supersedes any flag update from the multiplier operation.
Page 59: Multiplier Negative Flag (Mn)
Computation Units 2.6.5.2 Multiplier Negative Flag (MN) The negative flag is determined for all multiplier operations. MN is set whenever the result of a multiplier operation is negative. It is otherwise cleared. 2.6.5.3 Multiplier Overflow Flag (MV) Overflow is determined for all fixed-point and floating-point multiplier operations.
Page 60: Multiplier Instruction Summary
2 Computation Units 2.6.6 Multiplier Instruction Summary Instruction ASTAT Flags STKY Flags MU MN MV MI MUS MOS MVS MIS Fixed-Point = Rx * Ry – – – = MRF + Rx * Ry – – – = MRB MRF = MRF MRB = MRB = MRF –...
Page 61: Shifter
Computation Units Multiplier Instruction Summary, cont. Optional Modifiers for Fixed-Point: Signed input Unsigned input Integer input(s) Fractional input(s) Fractional inputs, Rounded output (SF) Default format for 1-input operations (SSF) Default format for 2-input operations SHIFTER The shifter operates on 32-bit fixed-point operands. Shifter operations include: •...
Page 62: Bit Field Deposit & Extract Instructions
2 Computation Units The X-input and Z-input are always 32-bit fixed-point values. The Y-input is a 32-bit fixed-point value or an 8-bit field (shf8), positioned in the register file as shown in Figure 2.4 below. Some shifter operations produce 8-bit or 6-bit results. These results are placed in either the shf8 field or the bit6 field (see Figure 2.5) and are sign- extended to 32 bits.
Page 63: Figure 2.6 Bit Field Deposit Instruction
Computation Units The FDEP (field deposit) instructions take a group of bits from the input register Rx (starting at the LSB of the 32-bit integer field) and deposit them anywhere within the result register Rn. The bit6 value specifies the starting bit position for the deposit.
Page 64: Figure 2.7 Bit Field Deposit Example
2 Computation Units The following field deposit instruction example is pictured in Figure 2.7: R0=FDEP R1 BY R2; R0=FDEP R1 BY R2; R1=0x000000FF00 R2=0x0000021000 0x0000 0210 00 00000000 00000000 010000 00000000 00000010 0 0 len6 = 8 len6 bit6 bit6 = 16 00000000 00000000 00000000 11111111 00000000...
Page 65: Figure 2.8 Bit Field Extract Example
Computation Units The following field extract instruction example is pictured in Figure 2.8: R3=FEXT R4 BY R5; R3=FEXT R4 BY R5; R4=0x8788000000 R5=0x0000021700 0x0000 0217 00 00000000 00000000 010111 00000000 00000010 0 0 len6 = 8 len6 bit6 bit6 = 23 10000000 00000000 00000000 00000000 10000111 0x8788 0000 00...
Page 66: Shifter Status Flags
2 Computation Units 2.7.3 Shifter Status Flags The shifter returns three status flags at the end of the operation. All of these flags appear in the ASTAT register. The SZ flag indicates if the output is zero, the SV flag indicates an overflow, and the SS flag indicates the sign bit in exponent extract operations.
Page 67: Shifter Instruction Summary
Computation Units 2.7.4 Shifter Instruction Summary Instruction Flags Rn = LSHIFT Rx BY Ry Rn = LSHIFT Rx BY <data8> Rn = Rn OR LSHIFT Rx BY Ry Rn = Rn OR LSHIFT Rx BY <data8> Rn = ASHIFT Rx BY Ry Rn = ASHIFT Rx BY<data8>...
Page 68: Multifunction Computations
2 Computation Units MULTIFUNCTION COMPUTATIONS In addition to the computations performed by each computation unit, the ADSP-2106x also provides multifunction computations that combine parallel operation of the multiplier and the ALU, or dual functions in the ALU. The two operations are performed in the same way as they are in corresponding single-function computations.
Page 69: Register File
Computation Units Register File R0 - F0 R1 - F1 R2 - F2 R3 - F3 Multiplier R4 - F4 R5 - F5 R6 - F6 R7 - F7 Any Register Any Register R8 - F8 R9 - F9 R10 - F10 R11 - F11 R12 - F12 R13 - F13...
Page 70: Alternate (Secondary) Registers
2 Computation Units If the same register file location is specified as both the source of an operand and the destination of a result or memory fetch, the read occurs in the first half of the cycle and the write in the second half. Thus the old data is used as the operand before the location is updated with the new result data.
Page 71 Computation Units MODE1 Name Definition SRRFH Register file alternate select for R15-R8 (F15-F8) SRRFL Register file alternate select for R7-R0 (F7-F0) Note that there is one cycle of effect latency from the instruction setting the bit in MODE1 to when the alternate registers may be accessed. For example, BIT SET MODE1 SRRFL;...
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Page 73: Program Sequencing
Program Sequencing OVERVIEW Program flow in the ADSP-2106x is most often linear; the processor executes program instructions sequentially. Variations in this linear flow are provided by the following program structures, illustrated in Figure 3.1 on the following page: • Loops. One sequence of instructions is executed several times with zero overhead.
Page 74: Instruction Cycle
3 Program Sequencing Address: Instruction DO UNTIL JUMP Instruction Instruction Instruction Instruction Instruction Instruction N Times Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Linear Flow Loop Jump INTERRUPT CALL Instruction IDLE Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction...
Page 75: Program Sequencer Architecture
Program Sequencing These cycles are overlapping, or pipelined, as shown in Figure 3.2. In sequential program flow, when one instruction is being fetched, the instruction fetched in the previous cycle is being decoded, and the instruction fetched two cycles before is being executed. Thus, the throughput is one instruction per cycle.
Page 76: Figure 3.3 Program Sequencer Block Diagram
3 Program Sequencing LOOP LOGIC LOOP ADDRESS STACK INTERRUPTS ASTAT MODE1 INTERNAL PMD BUS LOOP COUNT INTERRUPT STACK LATCH STATUS INTERRUPT INTERRUPT STACK CONTROLLER INTERRUPT LOGIC INSTRUCTION MASK CACHE INTERRUPT LOOP MASK POINTER CONTROLLER INPUT FLAGS INSTRUCTION LATCH CONDITION LOGIC DAG2 PROGRAM COUNTER...
Page 77: Program Sequencer Registers & System Registers
Program Sequencing 3.1.2.1 Program Sequencer Registers & System Registers Table 3.1 lists the registers located in the program sequencer. The functions of these registers are described in subsequent sections of this chapter. All registers in the program sequencer are universal registers and are thus accessible to other universal registers as well as to data memory.
Page 78: Program Sequencer Operations
3 Program Sequencing PROGRAM SEQUENCER OPERATIONS This section gives an overview of the operation of the program sequencer. The various kinds of program flow are defined here and described in detail in subsequent sections. 3.2.1 Sequential Instruction Flow The program sequencer determines the next instruction address by examining both the current instruction being executed and the current state of the processor.
Page 79: Conditional Instruction Execution
Program Sequencing CONDITIONAL INSTRUCTION EXECUTION The program sequencer evaluates conditions to determine whether to execute a conditional instruction and when to terminate a loop. The conditions are based on information from the arithmetic status (ASTAT) register, mode control 1 (MODE1) register, flag inputs and loop counter. The arithmetic ASTAT bits are described in the previous chapter, Computation Units.
Page 80: Table 3.2 Condition & Loop Termination Codes
3 Program Sequencing No. Mnemonic Description True If ALU equal zero AZ = 1 ALU less than zero See Note 1 below ALU less than or equal zero See Note 2 below ALU carry AC = 1 ALU overflow AV = 1 Multiplier overflow MV = 1 Multiplier sign...
Page 81: Branches (Call, Jump, Rts, Rti)
Program Sequencing BRANCHES (CALL, JUMP, RTS, RTI) The CALL instruction initiates a subroutine. Both jumps and calls transfer program flow to another memory location, but a call also pushes a return address onto the PC stack so that it is available when a return from subroutine instruction is later executed.
Page 82: Delayed & Nondelayed Branches
3 Program Sequencing 3.4.1 Delayed & Nondelayed Branches An instruction modifier (DB) indicates that a branch is delayed; otherwise, it is nondelayed. If the branch is nondelayed, the two instructions after the branch, which are in the fetch and decode stages, are not executed (see Figure 3.4);...
Page 83: Figure 3.5 Delayed Branches
Program Sequencing In a delayed branch, the processor continues to execute two more instructions while the instruction at the branch address is fetched and decoded (see Figure 3.5); in the case of a call, the return address is the third address after the branch instruction. A delayed branch is more efficient, but it makes the code harder to understand because of the instructions between the branch instruction and the actual branch.
Page 84: Pc Stack
3 Program Sequencing Because of the instruction pipeline, a delayed branch instruction and the two instructions that follow it must be executed sequentially. Instructions in the two locations immediately following a delayed branch instruction may not be any of the following: •...
Page 85: Loops (Do Until)
Program Sequencing The program counter stack pointer (PCSTKP) is a readable and writeable register that contains the address of the top of the PC stack. The value of PCSTKP is zero when the PC stack is empty, 1, 2, ..., 30 when the stack contains data, and 31 when the stack is overflowed.
Page 86: Restrictions & Short Loops
3 Program Sequencing LOOP-BACK CLOCK CYCLES Execute Instruction Decode Instruction Fetch Instruction termination loop start condition tests address is top of false PC stack LOOP TERMINATION CLOCK CYCLES Execute Instruction Decode Instruction Fetch Instruction termination loop-back aborts; condition tests PC and loop true stacks popped e = Loop end instruction...
Page 87: Counter-Based Loops
Program Sequencing • The last three instructions of a loop cannot be any branch (jump, call, or return); otherwise, the loop may not be executed correctly. This also applies to one-instruction loops and two-instruction loops with only one iteration. There is one exception to this rule, a non-delayed CALL (no DB modifier) paired with an RTS (LR), return from subroutine with loop reentry modifier.
Page 88: Non-Counter-Based Loops
3 Program Sequencing 3.5.1.3 Non-Counter-Based Loops A non-counter-based loop is one in which the loop termination condition is something other than LCE. When a non-counter-based loop is the outer loop of a series of nested loops, the end address of the outer loop must be located at least two addresses after the end address of the inner loop.
Page 89: Figure 3.8 Two-Instruction Counter-Based Loops
Program Sequencing Non-counter-based short loops terminate in a special way because of the fetch-decode-execute instruction pipeline: • In a three-instruction loop, the termination condition is tested when the top of loop instruction is executed. When the condition becomes true, the sequencer completes one full pass of the loop before exiting. •...
Page 90: Loop Address Stack
3 Program Sequencing 3.5.2 Loop Address Stack The loop address stack is six levels deep by 32 bits wide. The 32-bit word of each level consists of a 24-bit loop termination address, a 5-bit termination code, and a 2-bit loop type code: Bits Value 0-23...
Page 91: Loop Counters And Stack
Program Sequencing 3.5.3 Loop Counters And Stack The loop counter stack is six levels deep by 32 bits wide. The loop counter stack works in synchronization with the loop address stack; both stacks always have the same number of locations occupied. Thus, the same empty and overflow status flags apply to both stacks.
Page 92: Lcntr
3 Program Sequencing 3.5.3.2 LCNTR LCNTR is the value of the top of the loop counter stack plus one, i.e., it is the location on the stack which will take effect on the next loop stack push. To set up a count value for a nested loop without affecting the count value of the loop currently executing, you write the count value to LCNTR.
Page 93: Interrupts
Program Sequencing INTERRUPTS Interrupts are caused by a variety of conditions, both internal and external to the processor. An interrupt forces a subroutine call to a predefined address, the interrupt vector. The ADSP-2106x assigns a unique vector to each type of interrupt. Externally, the ADSP-2106x supports three prioritized, individually maskable interrupts, each of which can be either level or edge- triggered.
Page 94: Interrupt Latency
3 Program Sequencing At the end of the interrupt service routine, the RTI instruction causes the following actions: 1. Returns to the address stored at the top of the PC stack. 2. Pops this value off of the PC stack. 3.
Page 95: Figure 3.10 Interrupt Handling
Program Sequencing INTERRUPT, SINGLE-CYCLE INSTRUCTION n = Single-cycle instruction CLOCK CYCLES Execute Instruction Decode n+1->nop n+2->nop Instruction Fetch Instruction interrupt occurs interrupt n+1 pushed onto recognized PC stack; interrupt vector output INTERRUPT, PROGRAM MEMORY DATA ACCESS WITH CACHE MISS n = Instruction coinciding with program memory data access, cache miss CLOCK CYCLES...
Page 96: Interrupt Vector Table
3 Program Sequencing If nesting is enabled and a higher priority interrupt occurs immediately after a lower priority interrupt, the service routine of the higher priority interrupt is delayed by one additional cycle. (See “Interrupt Nesting & IMASKP”.) This allows the first instruction of the lower priority interrupt routine to be executed before it is interrupted.
Page 97: Table 3.3 Interrupt Vectors & Priority
Program Sequencing IRPTL/ IMASK Vector Interrupt Bit # Address* Name** Function 0x00 – reserved 0x04 RSTI Reset (read-only, non-maskable) HIGHEST PRIORITY 0x08 – reserved 0x0C SOVFI Status stack or loop stack overflow or PC stack full 0x10 TMZHI Timer=0 (high priority option) 0x14 VIRPTI Vector Interrupt...
Page 98: Interrupt Latch Register (Irptl)
3 Program Sequencing The interrupt vector table may be located in internal memory, at address 0x0002 0000 (the beginning of Block 0), or in external memory at address 0x0040 0000. If the ADSP-2106x’s on-chip memory is booted from an external source, the interrupt vector table will be located in internal memory.
Page 99: Interrupt Priority
Program Sequencing 3.6.4 Interrupt Priority The interrupt bits in IRPTL are ordered by priority. The interrupt priority is from 0 (highest) to 31 (lowest). Interrupt priority determines which interrupt is serviced first when more than one occurs in the same cycle. It also determines which interrupts are nested when nesting is enabled (see “Interrupt Nesting and IMASKP”).
Page 100: Interrupt Nesting & Imaskp
3 Program Sequencing After reset, all interrupts except for the reset interrupt and the EP0I interrupt for external port DMA Channel 6 (bit 16 of IMASK) are masked. The reset interrupt is always non-maskable. The EP0I interrupt is automatically unmasked after reset if the ADSP-2106x is booting from EPROM or from a host.
Page 101: Status Stack Save & Restore
Program Sequencing If nesting is not enabled, the processor masks out all interrupts and IMASKP is not used, although IMASKP is still updated to create a temporary interrupt mask. IRPTL is updated, but the ADSP-2106x does not vector to an interrupt that occurs while its service routine is already executing.
Page 102: Clearing The Current Interrupt For Reuse
3 Program Sequencing 3.6.8 Clearing The Current Interrupt For Reuse Normally the ADSP-2106x ignores and does not latch an interrupt that reoccurs while its service routine is already executing. When the interrupt initially occurs, the corresponding bit in IRPTL is set. During execution of the service routine, this bit is kept cleared—the ADSP-2106x clears the bit during every cycle, preventing the same interrupt from being latched while its service routine is already...
Page 103: External Interrupt Timing & Sensitivity
Program Sequencing Note that the JUMP(PC,3)(DB,CI) instruction actually only continues linear execution flow by jumping to the location PC + 3 (instr5), with the two intervening instructions (instr3, instr4) being executed because of the delayed branch (DB). This JUMP instruction is only an example—a JUMP (CI) can be to any location.
Page 104: Asynchronous External Interrupts
3 Program Sequencing 3.6.9.1 Asynchronous External Interrupts The processor accepts interrupts that are asynchronous to the ADSP- 2106x clock; that is, an interrupt signal may change at any time. An asynchronous interrupt must be held low at least one CLKIN cycle to guarantee that it is sampled.
Page 105: Timer
Program Sequencing TIMER The ADSP-2106x includes a programmable interval timer which can generate periodic interrupts. You program the timer by writing values to its two registers and you control timer operation through a bit in the MODE2 register. An external output, TIMEXP, signals to other devices that the timer count has expired.
Page 106: Timer Enable/Disable
3 Program Sequencing The TCOUNT register contains the timer counter. The timer decrements the TCOUNT register each clock cycle. When the TCOUNT value reaches zero, the timer generates an interrupt and asserts the TIMEXP output high for 4 cycles (when the timer is enabled).
Page 107: Timer Interrupts
Program Sequencing TIMER ENABLE Set TIMEN in MODE2 Timer Active CLOCK TCOUNT = N TCOUNT = N TCOUNT = N – 1 TIMER DISABLE Clear TIMEN in MODE2 Timer Inactive CLOCK TCOUNT = M – 1 TCOUNT = M – 2 TCOUNT = M –...
Page 108: Timer Registers
3 Program Sequencing Like other interrupts, the timer interrupt requires two cycles to fetch and decode the first instruction of the service routine. The service routine begins executing four cycles after the timer count reaches zero, as shown in Figure 3.14. CLOCK EXECUTE TCOUNT = 1...
Page 109: Idle & Idle16
Program Sequencing The status stack flags are read-only. Writes to the STKY register have no effect on these bits. The overflow and full flags are provided for diagnostic aid only and are not intended to allow recovery from overflow. Status stack or loop stack overflow or PC stack full causes an interrupt.
Page 110: Instruction Cache
3 Program Sequencing 3.10 INSTRUCTION CACHE The ADSP-2106x’s on-chip instruction cache is a 2-way, set-associative cache with entries for 32 instructions. Operation of the cache is transparent to the programmer. The ADSP-2106x caches only instructions that conflict with program memory data accesses (over the PM Data Bus, with the address generated by DAG2 on the PM Address Bus).
Page 111: Cache Efficiency
Program Sequencing LRU Bit Instruction Address Valid Bit Set 0 Set 1 Set 2 Set 13 Set 14 Set 15 Figure 3.15 Instruction Cache Architecture that set, it checks the addresses of the two entries to see whether either contains the needed instruction. A cache hit occurs if the instruction is found, and the LRU bit is updated if necessary to indicate the entry that did not contain the needed instruction.
Page 112: Figure 3.16 Cache-Inefficient Code
3 Program Sequencing When a cache miss occurs, the needed instruction is loaded into the cache so that if the same instruction is needed again, it will be there (i.e. a cache hit will occur). However, if another instruction whose address is mapped to the same set displaces this instruction, there will be a cache miss instead.
Page 113: Cache Disable & Cache Freeze
Program Sequencing 3.10.3 Cache Disable & Cache Freeze Freezing the cache prevents any changes to its contents—a cache miss will not result in a new instruction being stored in the cache. Disabling the cache stops its operation completely; all instruction fetches conflicting with program memory data accesses are delayed by the access.
Page 114 3 Program Sequencing 3 – 42 www.BDTIC.com/ADI...
Page 115: Chapter 4 Data Addressing
Data Addressing OVERVIEW The ADSP-2106x’s two data address generators (DAGs) simplify the task of organizing data by maintaining pointers into memory. The DAGs allow the processor to address memory indirectly; that is, an instruction specifies a DAG register containing an address instead of the address value itself. Data address generator 1 (DAG1) generates 32-bit addresses on the DM Address Bus.
Page 116: Figure 4.1 Data Address Generator Block Diagram
4 Data Addressing Each DAG contains eight of each type of register: DAG1 registers (32-bit) DAG2 registers (24-bit) B0-B7 B8-B15 I0-I7 I8-I15 M0-M7 M8-M15 L0-L7 L8-L15 DM Data Bus DAG1: N=32 DAG2: N=24 FROM INSTRUCTION Registers Registers Registers Registers 8 x N 8 x N 8 x N 8 x N...
Page 117: Alternate Dag Registers
Data Addressing 4.2.1 Alternate DAG Registers Each DAG register has an alternate (secondary) register for context switching. For activating alternate registers, each DAG is organized into high and low halves, as shown in Figure 4.2. The high half of DAG1 contains the I, M, B and L registers numbered 4-7, and the low half, the registers numbered 0-3.
Page 118: Dag Operation
4 Data Addressing Several control bits in the MODE1 register determine for each half whether primary or alternate registers are active (0=primary registers, 1=alternate registers): MODE1 Name Definition SRD1H DAG1 alternate register select (4-7) SRD1L DAG1 alternate register select (0-3) SRD2H DAG2 alternate register select (12-15) SRD2L...
Page 119: Dag Modify Instructions
Data Addressing PRE-MODIFY POST-MODIFY Without I Register Update With I Register Update PM (Mx, Ix) PM (Ix, Mx) DM (Mx, Ix) DM (Ix, Mx) 1. output 2. update I + M I + M output Figure 4.3 Pre-Modify & Post-Modify Operations 4.3.1.1 DAG Modify Instructions In ADSP-2106x assembly language, pre-modify and post-modify operations are distinguished by the positions of the index and modifier...
Page 120: Immediate Modifiers
4 Data Addressing Any M register can modify any I register within the same DAG (DAG1 or DAG2). Thus, DM(M0,I2) = TPERIOD; is a legal instruction that accesses the data memory location M0 + I2; however, DM(M0,I14) = TPERIOD; is not a legal instruction because the I and M registers belong to different DAGs.
Page 121: Circular Buffer Operation
Data Addressing Length = 11 Base address = 0 Modifier (step size) = 4 Sequence shows order in which locations are accessed in one pass. Sequence repeats on subsequent passes. Figure 4.4 Circular Data Buffers 4.3.2.1 Circular Buffer Operation You set up a circular buffer in assembly language by initializing an L register with a positive, nonzero value and loading the corresponding (same-numbered) B register with the base (starting) address of the buffer.
Page 122: Circular Buffer Registers
4 Data Addressing If M is positive, if I + M < Buffer base + length (end of buffer) + M ≥ Buffer base + length (end of buffer) + M – L if I If M is negative, + M ≥ Buffer base (start of buffer) if I + M + L if I...
Page 123 Data Addressing Whenever a circular buffer addressing operation using these registers causes the address in the I register to be incremented (or decremented) past the end (or start) of the circular buffer, an interrupt is generated. Depending on which register set was used, the interrupt is either: DAG Registers Vector Symbolic...
Page 124: Bit-Reversal
4 Data Addressing 4.3.3 Bit-Reversal Bit-reversal of memory addresses can be performed in two ways: by enabling the bit-reverse mode on DAG1 or DAG2 and using a specific I register (I0 or I8), or by using the explicit bit-reverse instruction (BITREV). 4.3.3.1 Bit-Reverse Mode In bit-reverse mode, DAG1 bit-reverses 32-bit address values output from I0 and DAG2 bit-reverses 24-bit address values output from I8.
Page 125: Dag Register Transfers
Data Addressing DAG REGISTER TRANSFERS DAG registers are part of the universal register set and may be written to from memory, from another universal register, or from an immediate field in an instruction. DAG register contents may be written to memory or to a universal register.
Page 126: Dag Register Transfer Restrictions
4 Data Addressing 4.4.1 DAG Register Transfer Restrictions For certain instruction sequences involving transfers to and from DAG registers, an extra (NOP) cycle is automatically inserted by the processor (1). Certain other sequences cause incorrect results and are not allowed by the ADSP-21000 Family assembler (2).
Page 127: Chapter 5 Memory
Memory OVERVIEW ADSP-2106x processors contain a large dual-ported memory for on- chip program and data storage. On these processors, the two memory blocks are named Block 0 and Block 1. A comparison of on-chip memory (SRAM) available on ADSP-2106x processors is as follows: On-chip SRAM ADSP-21060 ADSP-21062...
Page 128: Figure 5.1 Adsp-2106X Block Diagram
5 Memory With this dual-ported structure, accesses of internal memory by the processor core and I/O processor are independent and transparent to one another. Each block of memory can be accessed by both the core processor and the I/O processor in every cycle—no extra cycles are incurred when both the core and the I/O processor access the same block.
Page 129: Dual Data Accesses
Memory Both the core processor and I/O processor have access to the external bus (DATA , ADDR ), via the ADSP-2106x’s external port. The external 47-0 31-0 port provides access to off-chip memory and peripherals; it can also access the internal memory of other ADSP-2106xs connected in a multiprocessing system.
Page 130: Instruction Cache & Pm Bus Data Accesses
5 Memory This means that for an instruction requiring two data accesses, the PM bus (and DAG2) is used to access data from the mixed block, the DM bus (and DAG1) is used to access data from the data-only block, and the instruction to be fetched must be available from the cache.
Page 131: On-Chip Memory Buses & Address Generation
Memory By providing the instruction, the cache lets the core processor access data over the PM bus—the core processor fetches the instruction from the cache instead of from memory so that the processor can simultaneously transfer data over the PM bus. Only the instructions whose fetches conflict with PM bus data accesses are cached.
Page 132: Bus Exchange (Px Registers)
5 Memory The PX bus connect registers permit data to be passed between the 48-bit PM Data bus and the 40-bit DM Data bus or between the 40-bit register file and the PM Data bus. These registers contain hardware to handle the 8-bit width difference.
Page 133: Figure 5.3 Px Register Transfers
Memory PM Data Bus Transfers DM Data Bus or Register File Transfers 16 ZEROS 8 ZEROS 16 ZEROS 16 ZEROS 16 ZEROS 8 ZEROS Register File PX Register PX Register To Internal Memory 8 ZEROS PX Register To External Memory PX Register Figure 5.3 PX Register Transfers 5 –...
Page 134: Memory Block Accesses & Conflicts
5 Memory When the combined PX register is used for PM Data Bus transfers, the entire 48 bits can be read from or written to program memory. PX2 contains the 32 MSBs of the 48-bit word while PX1 contains the 16 LSBs.
Page 135: Adsp-2106X Memory Map
Memory ADSP-2106x MEMORY MAP The ADSP-2106x memory map, shown in Figure 5.5, is divided into three sections: internal memory space, multiprocessor memory space, and external memory space. Internal memory space consists of the ADSP-2106x’s on-chip memory and resources. Multiprocessor memory space corresponds to the on-chip memory and resources of other ADSP-2106x’s in a multiprocessor system.
Page 136: Figure 5.5 Adsp-2106X Memory Map
5 Memory 0x0040 0000 0x0000 0000 IOP Registers Internal 0x0002 0000 Memory Normal Word Addressing Space 0x0004 0000 Bank 0 Short Word Addressing 0x0008 0000 Internal Memory Space of ADSP-2106x with ID=001 0x0010 0000 Bank 1 Internal Memory Space of ADSP-2106x with ID=010 0x0018 0000 Internal Memory Space...
Page 137: Adsp-21060 Internal Memory Space
Memory The ADSP-2106x’s I/O processor monitors the addresses of all memory accesses and routes them to the appropriate memory space. The E (external), M (multiprocessing), and S fields are decoded by the I/O processor as shown below. If the E bit field is all zeros, the M and S fields become active and are decoded.
Page 138: Figure 5.6 Adsp-21060 Internal Memory Space
5 Memory 0x0000 0000 IOP Registers 0x0000 0100 Reserved Address Space These represent the same physical memory (4 MBits) 0x0001 FFFF 0x0002 0000 0x0004 0000 Block 0 0x0003 0000 Block 0 Block 1 0x0003 FFFF Normal Word Addressing 0x0006 0000 128K x 32-bit Words 80K x 48-bit Words When addressed as 80K x 48-bit, there are...
Page 139: Table 5.1 Adsp-21060 Internal Memory Addresses
Memory 0x0000 0000 – 0x0000 00FF IOP Registers (control/status registers) 0x0000 0100 – 0x0001 FFFF Reserved addresses 0x0002 0000 – 0x0002 FFFF Block 0 – Normal Word Addressing (32-bit, 48-bit words) 0x0003 0000 – 0x0003 FFFF Block 1 – Normal Word Addressing (32-bit, 48-bit words) 0x0004 0000 –...
Page 140: Adsp-21062 Internal Memory Space
5 Memory The ADSP-2106x’s interrupt vector table is located at the start of normal word addressing, 0x0002 0000 – 0x0002 007F, when the processor is booted from an external source (EPROM, host port, or link port booting). If the processor is in “no boot” mode, the interrupt vector table is located in external memory, 0x0040 0000 to 0x0040 007F.
Page 141: Figure 5.7A Adsp-21062 Internal Memory Space
Memory 0x0000 0000 IOP Registers 0x0000 0100 Reserved Address Space 0x0001 FFFF 0x0002 0000 Block 0 0x0004 0000 0x0002 8000 Block 1 Block 0 0x0003 0000 Block 1 Alias 0x0005 0000 0x0003 8000 Block 1 Alias Block 1 0x0003 FFFF Normal Word 0x0006 0000 Addressing...
Page 142: Adsp-21061 Internal Memory Space
5 Memory 5.2.3 ADSP-21061 Internal Memory Space The ADSP-21061 is a memory-variant version of the ADSP-21060. The two processors include the following amounts of on-chip SRAM: Total Maximum Maximum Processor Memory Data Memory Program Memory ADSP-21060 4 Mbits 128K x 32 80K x 48 ADSP-21062 1 Mbits...
Page 143: Figure 5.7B Adsp-21061 Internal Memory Space
Memory 0x0000 0000 IOP Registers 0x0000 0100 Reserved Address Space 0x0001 FFFF 0x0002 0000 Block 0 0x0002 4000 0x0004 0000 Block 1 Block 0 0x0002 8000 Block 1 Alias 0x0004 8000 0x0002 C000 Block 1 Block 1 Alias 0x0003 0000 0x0005 0000 Block 1 Alias Block 1...
Page 144: Porting Code From Adsp-21060 To Adsp-21062 Or Adsp-21061
5 Memory 5.2.4 Porting Code from ADSP-21060 to ADSP-21062 or ADSP-21061 To ease porting code between ADSP-2106x processor, a system for aliasing memory Block 1 eliminates the need to re-arrange (some) code placement. For example, memory Block 0 on the ADSP-21062 starts at the beginning of internal memory, normal word address 0x0002 0000.
Page 145: External Memory Space
Memory (M=ID =000). Addresses with M=ID =000 are only allowed in single-processor systems. If the ADSP-2106x attempts to access an invalid address in multiprocessor memory space, data written will be ignored and reads will return invalid data. For additional information about multiprocessor memory accesses, see “Direct Reads &...
Page 146: Internal Memory Organization & Word Size
5 Memory INTERNAL MEMORY ORGANIZATION & WORD SIZE The ADSP-2106x’s internal SRAM memory accommodates the following word types: • 48-bit instructions • 32-bit floating-point data • 16-bit short word data 40-bit extended-precision floating-point data values are also accommodated, but are accessed in 48-bit words. The 40 bits are left- justified in the 48-bit word (bits 47-8).
Page 147 Memory When an address is applied to memory for a read or write, the particular columns selected depends upon the word width of the access. For 48-bit words, the 16-bit columns are selected in groups of three. In a memory block consisting entirely of 48-bit instruction words, 16 columns ÷...
Page 148: Figure 5.8 Memory Organization Vs. Address (Adsp-21060)
5 Memory ADSP-21060 (Two blocks of 8Kx16-bit columns) Block 0 |--------------|--------------|--------------|--------------|--------------|----| 48-bit words |--------------|--------------|--------------|--------------|--------------|----| 0x20000 0x22000 0x24000 0x26000 0x28000 |---------|---------|---------|---------|---------|---------|---------|---------| 32/16-bit words |---------|---------|---------|---------|---------|---------|---------|---------| 0x20000 0x22000 0x24000 0x26000 0x28000 0x2a000 0x2c000 0x2e000 Block 1 |--------------|--------------|--------------|--------------|--------------|----| 48-bit words |--------------|--------------|--------------|--------------|--------------|----| 0x30000 0x32000 0x34000 0x36000 0x38000 |---------|---------|---------|---------|---------|---------|---------|---------|...
Page 149: Mixing 32-Bit & 48-Bit Words In One Memory Block
Memory ADSP-21061 (Two blocks of 4Kx16-bit columns) Block 0 |--------------|--------------|---------| 48-bit words |--------------|--------------|---------| 0x20000 0x21000 0x22000 |---------|---------|---------|---------| 32/16-bit words |---------|---------|---------|---------| 0x20000 0x21000 0x22000 0x23000 Block 1 |--------------|--------------|---------| 48-bit words |--------------|--------------|---------| 0x24000 0x25000 0x26000 |---------|---------|---------|---------| 32/16-bit words |---------|---------|---------|---------| 0x24000 0x25000 0x26000 0x27000 Figure 5.9b Memory Organization vs.
Page 150: Basic Examples Of Mixed 32-Bit & 48-Bit Words
5 Memory 5.3.3 Basic Examples Of Mixed 32-Bit & 48-Bit Words Each block of memory is physically organized as 16 columns, each 16 bits wide, with a height of 8K on the ADSP-21060 and 4K on the ADSP-21062. Figure 5.10 illustrates four basic combinations of mixed 48-bit instructions and 32-bit data within a single block: A.
Page 151: Figure 5.10 Basic Examples Of Mixed Instructions & Data In A Memory Block
Memory 32-bit data must start on an even column 1 column=16 bits (ADSP-21060) 8K (ADSP-21062) 4K 3 columns for 12 columns for 32-bit data 48-bit instructions 48K Data (ADSP-21060) 8K Instructions (ADSP-21060) 24K Data (ADSP-21062) 4K Instructions (ADSP-21062) (ADSP-21060) 8K (ADSP-21062) 4K 6 columns for 48-bit instructions 10 columns for 32-bit data...
Page 152: Table 5.3 Address Ranges For Instructions & Data (Adsp-21060)
5 Memory Table 5.3 shows the addressing in Block 0 (beginning address = 0x0002 0000) for each of the instruction and data combinations of Figure 5.10, on the ADSP-21060: 48-Bit Instructions 32-Bit Data start address end address start address end address 0x0002 0000 0x0002 1FFF 0x0002 4000...
Page 153: Bit Short Words
Memory To determine the starting address of the 32-bit data, the following equations are used (for the ADSP-21062 and ADSP-21061): Starting Address of 32-Bit Data B + 4K + m + 1 B + 8K + m + 1 B + 16K + m + 1 B + 20K + m + 1 B = beginning address of memory block n = number of 48-bit instruction word locations...
Page 154: Mixing 32-Bit & 48-Bit Words With Finer Granularity
5 Memory 32-Bit Normal Words Addr 2 Addr 5 Addr 4 Addr 3 Addr 2 Addr 1 Addr 0 Addr 1 Addr 0 16-Bit 16-Bit Short Short Words Words DATA 31-16 Figure 5.11 Short Word Addresses 16-bit short words read into ADSP-2106x registers are automatically extended into 32-bit integers.
Page 155: Low-Level Physical Mapping Of Memory Blocks
Memory 5.3.5.1 Low-Level Physical Mapping Of Memory Blocks Each block of memory is organized as 16 columns. On the ADSP-21060, each column contains 8K 16-bit words; on the ADSP-21062, each column contains 4K 16-bit words. For reads or writes of 48-bit and 32-bit words, the 13 LSBs of the address select a row from each column.
Page 156: Placement Restrictions For Mixed 32-Bit & 48-Bit Words
5 Memory 5.3.5.2 Placement Restrictions For Mixed 32-Bit & 48-Bit Words 32-bit and 48-bit words are grouped differently within a memory block and try to use the same address area. This may cause errors when mixing 48-bit instructions and 32-bit data within the same block. (Since 32-bit and 16-bit words use the same grouping structure and different addresses, they can be freely mixed within a memory block.) The overall guideline for placement of mixed word sizes is that all 48-bit...
Page 157 Memory Odd Number of 48-Bit Column Groups (1000 48-Bit Words ) Addr 8191 Addr 8191 Addr 16383 Addr 16383 ... . Usable but Noncontiguous 48-Bit Words 32-Bit Words ..
Page 158 5 Memory Odd Number of 48-Bit Column Groups (1000 48-Bit Words) Addr 4095 Addr 4095 Addr 8191 Addr 8191 ... . Usable but Noncontiguous 48-Bit Words 32-Bit Words ..
Page 159: Shadow Write Fifo
Memory To determine, however, exactly which addresses are valid again requires an analysis of how the data is placed in memory. The simplest solution is to think of the 16-bit words as being mapped into 32-bit word space and allocate memory with the same method described above for 32-bit words.
Page 160: Configuring Memory For 32-Bit Or 40-Bit Data
5 Memory If 48-bit accesses and 32-bit accesses to the same locations absolutely must be mixed in this way, you must flush out the shadow FIFO with two dummy writes before attempting to read the data. 5.3.6 Configuring Memory For 32-Bit or 40-Bit Data Each block of internal memory can be configured to store either single- precision 32-bit data or extended-precision 40-bit data.
Page 161: External Memory Interfacing
Memory EXTERNAL MEMORY INTERFACING In addition to its on-chip SRAM, the ADSP-2106x provides addressing of up to 4 gigawords of off-chip memory through its external port. This external address space includes multiprocessor memory space, the on-chip memory of all other ADSP-2106xs connected in a multiprocessor system, as well as external memory space, the region for standard addressing of off-chip memory.
Page 162: Table 5.7 External Memory Interface Signals
5 Memory The internal 32-bit DM Address bus and the I/O processor can access the entire 4-gigaword external memory space. The 24-bit PM Address bus, however, can only access 12 megawords of external memory because of its smaller width. Type Function ADDR I/O/T...
Page 163 Memory Type Function I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP- 2106x writes to external memory devices or to the internal memory of other ADSP-2106xs. External devices must assert to write to the ADSP-2106x’s internal memory. In a multiprocessing system is output by the bus master and is input by all other ADSP- 2106xs.
Page 164: External Memory Banks
5 Memory 5.4.1 External Memory Banks External memory is divided into four banks of equal size, each associated with its own wait-state generator. This allows slower peripheral devices to be memory-mapped into a bank for which a specific number of wait states are specified. By mapping peripherals into different banks, you can accommodate I/O devices with different timing requirements.
Page 165: Boot Memory Select (Bms)
Memory 5.4.3 Boot Memory Select ( memory select line is asserted (low) only when the ADSP- 2106x is configured for EPROM booting. This allows access of a separate external memory space for booting. Unbanked memory wait states and wait state mode are applied to -selected accesses.
Page 166: Wait Register
5 Memory • Either. The ADSP-2106x completes the cycle as soon as it samples the ACK input as high or when the WAIT-programmed number of wait states have expired, whichever occurs first. In this mode, a system with two different types of peripherals could shorten the access for the faster peripheral using ACK but use the programmed wait states for the slower peripheral.
Page 167: Table 5.8 Wait Register Bit Definitions
Memory Bit(s) Name Function EB0WM External Bank 0 wait state mode* EB0WS External Bank 0 number of wait states** EB1WM External Bank 1 wait state mode* EB1WS External Bank 1 number of wait states** 11-10 EB2WM External Bank 2 wait state mode* 14-12 EB2WS External Bank 2 number of wait states**...
Page 168: Figure 5.15 Wait Register
5 Memory 30 29 25 24 HIDMA EB3WS Handshake Idle Cycle for DMA Ext. Bank 3 Number of Waitstates MMSWS UBWM Multiprocessor Memory Space Waitstate Unbanked Memory Waitstate Mode PAGEIS UBWS Page Boundary Crossing Idle Cycle Unbanked Memory Number of Waitstates PAGSZ Page Size (for DRAM) 15 14...
Page 169: Figure 5.16 Bus Idle Cycle, Hold Time Cycle, Page Idle Cycle
Memory Bus Idle Cycle Address changes here ADDR Access Bus Idle Read from different Cycle bank or unbanked, or a write Hold Time Cycle Address changes here ADDR RD/WR DATA (for WR) Hold Time Access Cycle Page Idle Cycle Address changes here ADDR RD/WR PAGE...
Page 170: Multiprocessor Memory Space Wait States & Acknowledge
5 Memory 5.4.4.2 Multiprocessor Memory Space Wait States & Acknowledge Completion of reads and writes to multiprocessor memory space depends only on the ACK signal. This is facilitated by using the signal as an early indication of whether the access is a write or a read (see Figure 5.19 at the end of this chapter), as well as the use of the automatic wait state option for multiprocessor memory space—the MMSWS bit of the WAIT register.
Page 171 Memory PAGSZ DRAM Page Size 256 words 512 words 1024 words (1K) 2048 words (2K) 4096 words (4K) 8192 words (8K) 16384 words (16K) 32768 words (32K) The ADSP-2106x asserts its PAGE pin whenever an external access crosses a page boundary and the address is within bank 0. The processor detects a boundary crossing by comparing each address output for bank 0 to the address of the last successful external access (which is stored in the IOP register ELAST).
Page 172: Figure 5.17 Example Dram Interface
5 Memory The host bus request pin ( ) is disabled when the PAGE pin is asserted. This prevents the possibility of the ADSP-2106x becoming a bus slave (by means of the deadlock resolution functionality) while the DRAM controller is servicing a page change. (See “Suspend Bus Tristate”...
Page 173 Memory SBTS SBTS 5.4.5.1 Suspend Bus Tristate ( SBTS External devices can assert the ADSP-2106x’s input to place the external bus address, data, selects, and strobes in a high-impedance state for the following cycle. If the ADSP-2106x attempts to access SBTS external memory while is asserted, the processor will halt and...
Page 174: External Memory Access Timing
5 Memory EXTERNAL MEMORY ACCESS TIMING Memory access timing for external memory space and multiprocessor memory space is described below. For exact timing specifications, refer to the ADSP-2106x Data Sheet. 5.5.1 External Memory The ADSP-2106x can interface asynchronously, without reference to CLKIN, to external memories and and memory-mapped peripherals.
Page 175: External Memory Write – Bus Master
Memory CLOCK ADDRESS Read Address / Write Address MSx , SW RD or WR DATA Read Data / Write Data Figure 5.18 External Memory Access Timing Note that if a memory read is part of a conditional instruction that is not executed because the condition is false, the ADSP-2106x still drives the address and memory select for the read, but does not assert the read strobe or read any data.
Page 176: Multiprocessor Memory
5 Memory 3. The ADSP-2106x checks whether wait states are needed. If so, the memory select and write strobe remain active for additional cycle(s). Wait states are determined by the state of the external acknowledge signal, the internally programmed wait state count, or a combination of the two.
Page 177: Figure 5.19 Multiprocessor Memory Access Timing
Memory Clock Cycles ADDRESS Write Address Write Address Read Address (Output by slave, Slave holds ACK Slave holds ACK Input to master) low for 1 cycle low for 2 cycles DATA Write Data Write Data Read Data ADSP-2106x Master Master Master Master Master...
Page 178 5 Memory 5 – 52 www.BDTIC.com/ADI...
Page 179: Overview
OVERVIEW Direct Memory Access (DMA) provides a mechanism for transferring an entire block of data. The ADSP-2106x’s on-chip DMA controller relieves the core processor of the burden of moving data between internal memory and an external data source or external memory. The fully integrated DMA controller allows the ADSP-2106x core processor, or an external device, to specify data transfer operations and return to normal processing while the DMA controller carries out the...
Page 180: Figure 6.1 Adsp-2106X Block Diagram
6 DMA Internal Memory PROCESSOR PORT I/O PORT ADDR DATA DATA ADDR Core Processor External Port PM Address Bus (PMA) 24 Addr ADDR DM Address Bus (DMA) 32 31-0 HOST INTERFACE PM Data Bus (PMD) Data DATA DM Data Bus (DMD) 32/40 47-0 CONTROLLER...
Page 181: Figure 6.2 Dma Data Paths & Control
Core Internal Memory Processor PM Address Addr DM Address Addr Addr Data Data Data External Port PM Data DM Data Slave Write FIFO (Async writes - 4 deep) ADDR 31-0 (Sync writes - 2 deep) DATA Buffer 47-0 I/O Data I/O Address Ext.
Page 182: Table 6.1A Adsp-2106X Dma Channels & Data Buffers
6 DMA The ten DMA channels of the ADSP-21060 and ADSP-21062 are numbered as shown in Table 6.1a, which also shows the corresponding data buffer used with each channel. Data Channel# Buffer Description DMA Channel 0 Serial Port 0 Receive DMA Channel 1 RX1 (or LBUF0) Serial Port 1 Receive (or Link Buffer 0)
Page 183: Dma Controller Features
The following terms are used throughout this chapter, and are defined below for reference: external port FIFO buffers EPB0, EPB1, EPB2, and EPB3—the IOP registers used for external port DMA transfers and single-word data transfers (from other ADSP-2106xs or from a host processor);...
Page 184: Setting Up Dma Transfers
6 DMA I/O port DMA transfers handle data transmitted and received through the ADSP-2106x’s serial ports and link ports. When performing I/O DMA, the same type of buffer is set up in internal memory, but instead of accessing the external memory, the DMA controller accesses the I/O port.
Page 185: Dma Control Registers
DMA interrupts are latched and masked in the IRPTL and IMASK registers, respectively; these registers are located in the ADSP-2106x processor core, not in the memory-mapped IOP register space. TO START A NEW DMA SEQUENCE AFTER THE CURRENT ONE IS FINISHED YOUR PROGRAM MUST FIRST CLEAR THE DMA ENABLE BIT WRITE NEW PARAMETERS TO THE II...
Page 186: Table 6.2 Dma Control, Buffer, & Parameter Registers
6 DMA Register Name(s) Width Description EPB0 External Port FIFO Buffer 0 EPB1 External Port FIFO Buffer 1 EPB2 External Port FIFO Buffer 2 EPB3 External Port FIFO Buffer 3 DMAC6 DMA Channel 6 Control Register (Ext. Port Buffer 0 or Link Buffer 4) 1, 2 DMAC7 DMA Channel 7 Control Register (Ext.
Page 187: External Port Dma Control Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 Ext. Port FIFO Buffer Status DMA Enable for Ext. Port 00=empty, 10=partially full, 11=full 1=enable, 0=disable CHEN FLSH DMA Chaining Enable for Ext. Port Flush Ext.
Page 188: Table 6.3 External Port Dma Control Registers (Dmacx)
6 DMA chained DMA operations, however, this is not necessary.) Bit(s) Name Definition DMA Enable for External Port CHEN DMA Chaining Enable for External Port TRAN Transmit/Receive (1=transmit, 0=receive) Pack Status (read-only) DTYPE Data Type (0=data, 1=instructions) PMODE Packing Mode (00=none, 01=16/32, 10=16/48, 11=32/48) MSWF Most Significant Word First during packing MASTER...
Page 189 TRAN Transmit (1) or Receive (0). (1=read from ADSP-2106x, 0=write to ADSP-2106x.) This bit specifies the data transfer direction as internal-to-external when set to 1. (When EXTERN=1, setting TRAN=1 specifies a read from external memory and TRAN=0 specifies a write to external memory.) PS is a two-bit status field that indicates whether the packing buffer is on its first, second, or last pack: Status...
Page 190 6 DMA FLSH Reinitializes the state of the DMA channel, clearing the FS and PS status bits to zero. The external port FIFO buffer and DMA request counter are flushed and any internal DMA states are reset. Any partially packed data words are also flushed. The entire flushing operation has a two-cycle latency.
Page 191 The MASTER, HSHAKE, and EXTERN bits configure the DMA mode in the following manner: M H E DMA Mode of Operation Slave Mode. The DMA request is generated whenever the receive buffer is not empty or the transmit buffer is not full. Reserved Handshake Mode.
Page 192: Serial Port Dma Control
6 DMA 6.2.2 Serial Port DMA Control The ADSP-2106x’s two serial ports, SPORT0 and SPORT1, can use DMA transfers to handle transmit and receive data. DMA channels 0-3 are assigned to the serial ports, with channels 1 and 3 for SPORT1 being shared with link buffers 0 and 1 on the ADSP-21060 and ADSP- 21062.
Page 193: Link Port Dma Control
The D2DMA bit places the DMA controller in two-dimensional SPORT DMA mode on the ADSP-21060 and ADSP-21062. Two-dimensional SPORT DMA mode is not applicable to the ADPS-21061. This bit should be cleared (to 0) for standard operation. Each serial port has a transmit DMA interrupt and a receive DMA interrupt.
Page 194: Table 6.8 Lctl Control Bits For Link Port Dma
6 DMA Link port DMA operations are set up in the DMA parameter registers for each channel. Table 6.2 lists these registers. Either 32- or 48-bit word widths can be used in link port DMA transfers. The link buffer DMA enable and control bits are located in the LCTL register.
Page 195: Port Selection For Shared Dma Channels
Interrupt Name Interrupt SPR1I DMA Channel 1 – SPORT1 Rx (or Link Buffer 0) SPT1I DMA Channel 3 – SPORT1 Tx (or Link Buffer 1) LP2I DMA Channel 4 – Link Buffer 2 LP3I DMA Channel 5 – Link Buffer 3 EP0I DMA Channel 6 –...
Page 196: Dma Channel Status Register (Dmastat)
6 DMA Channel 3 is assigned to either SPORT1 Transmit or Link Buffer 1 in the same way. Channel 6 is assigned to either External Port Buffer 0 or Link Buffer 4 according the following rules: • If the External Port DMA enable bit is set in the DMAC6 control register (DEN=1), then Channel 6 is assigned to EPB0.
Page 197: Table 6.10 Dmastat Register
Bit# Definition DMA Channel 0 Status DMA Channel 1 Status DMA Channel 2 Status DMA Channel 3 Status DMA Channel 4 Status 1, 3 DMA Channel 5 Status 1, 3 DMA Channel 6 Status DMA Channel 7 Status DMA Channel 8 Status 1, 3 DMA Channel 9 Status 1, 3...
Page 198: Dma Controller Operation
6 DMA As an alternative to interrupt-driven DMA, polling DMASTAT can be used to determine when a single DMA sequence has completed: 1. Read DMASTAT. 2. If both status bits for the channel are inactive, the DMA sequence has completed. If chaining is enabled, however, polling should not be used since the next DMA sequence may be under way by the time the polled status is returned.
Page 199: Dma Channel Parameter Registers
channel on itself by writing to its DMA control and parameter registers. The external port and link port DMA channels can be configured to transmit or receive data from internal memory. The serial port DMA channels, however, are unidirectional, either transmit or receive only. 6.3.1 DMA Channel Parameter Registers The DMA channels operate in a similar fashion as the ADSP-2106x’s...
Page 200 6 DMA that channel are not disabled. Rather, 2 transfers will be performed. This occurs because the first transfer is started before the count value is tested. The correct way to disable a DMA channel is to clear its DMA enable bit in the corresponding control register.
Page 201: Table 6.11 Dma Parameter Registers
Parameter Register Bits Function Internal Index (starting address for data buffer – 0x0002 0000) Internal Modifier (address increment) Internal Count (number of words to transfer) Chain Pointer (address of next set of buffer parameters) General-Purpose (or 2D DMA) External Index (Ext. Port DMA channels only) External Modifier (Ext.
Page 202: Internal Request & Grant
6 DMA local bus Address Generator Index (Address) Modifier Internal Only for 2-D DMA Memory Address Post-Modify local bus Word Counter Count Chain Pointer General Purpose – 1 For 2-D DMA Only for 2-D DMA working register Only for External Port DMA Channels local bus Address Generator...
Page 203: Dma Channel Prioritization
When a particular I/O port needs to write data to internal memory, it asserts its request. This request is prioritized with all other valid DMA requests. See Figure 6.2. When a channel becomes the highest priority requester, its internal grant is asserted by the DMA controller. In the next clock cycle, the DMA transfer is started.
Page 204: Rotating Priority For Ext. Port Channels
6 DMA The DMA controller determines the highest priority requesting channel during every cycle, between each individual data transfer. Master/slave bus request prioritization, however, occurs only when the ADSP-2106x master gives up control of the external bus—this occurs only after an entire DMA block transfer has completed. Note that external direct accesses of internal memory and TCB chain loading are prioritized along with the DMA channels.
Page 205: Figure 6.5 Rotating Priority Example (Adsp-21060 & Adsp-21062)
The external port channel priorities do not change relative to the serial port and link port channel priorities. At reset, the DCPR bit is cleared and rotating priority is disabled. Highest Highest Priority Priority One transfer occurs on Channel 7, which Lowest Lowest then rotates into the...
Page 206: Dma Chaining
6 DMA channels. The channel immediately after the selected channel will now have the highest fixed priority, for example (ADSP-21060 & ADSP-21062): HIGHEST LOWEST Priority at Reset: DMA6 DMA7 DMA8 DMA9 Follow steps 1-4 above to make DMA7 the lowest priority. New Priority Ordering: DMA8 DMA9...
Page 207: Figure 6.6 Chain Pointer Register & Pci Bit
The CP register is 18 bits wide, of which the lower 17 bits are the memory address field. The memory address field is offset by 0x0002 0000 before it is used by the DMA controller. The most significant bit (bit 17) of the CP register is a control bit called PCI (Program-Controlled Interrupts).
Page 208: Transfer Control Blocks & Chain Loading
6 DMA 6.3.4.1 Transfer Control Blocks & Chain Loading During TCB chain loading, the DMA channel parameter registers are loaded with values retrieved from internal memory. The CP register contains the chain pointer—the highest address of the TCB. The TCB is stored in consecutive locations.
Page 209: Setting Up & Starting The Chain
When the chain loading is complete, the working register is loaded with the new CP value. This allows chained DMA sequences to be set up in a continuous loop. (Note: The contents of the working register are not accessible.) TCB chain loading is requested like all other DMA operations. A TCB loading request is latched and held in the DMA controller until it becomes the highest priority request.
Page 210: Chain Insertion
6 DMA The DMA controller will autoinitialize itself with the first TCB and then start the first transfer. When this transfer is completed, the next one will begin if the current chain pointer address is non-zero. This address will be used as the pointer to the next TCB. Remember that the address field of the CPx registers is only 17 bits wide.
Page 211: Dma Interrupts
6.3.5 DMA Interrupts When the count register (C) of an active DMA channel decrements to zero, an interrupt is generated. For the external port DMA channels, both the C and EC (external count) registers must equal zero before the interrupt is generated (EC register only in MASTER mode). The count register(s) must be decremented to zero as a result of actual DMA transfers in order for a DMA interrupt to be generated—writing zero to a count register will not generate the interrupt.
Page 212 6 DMA chaining is disabled, the IMASK register must be used to disable interrupts. Interrupt requests enabled by PCI can still be masked out by the IMASK register. DMA interrupts can also be generated by ADSP-2106x’s I/O ports without using DMA. In this case, a DMA interrupt is generated whenever data becomes available at the receive buffer, or whenever the transmit buffer does not have new data to transmit.
Page 213: Starting & Stopping Dma Sequences
If chaining is enabled, however, polling DMASTAT should not be used since the next DMA sequence may be under way by the time the polled status is returned. 6.3.6 Starting & Stopping DMA Sequences DMA sequences are started in different ways depending on whether DMA chaining is enabled.
Page 214: External Port Dma
6 DMA restart at the new count. EXTERNAL PORT DMA Channels 6, 7, 8, and 9 are the external port DMA channels, which are available on the ADSP-21060 and ADSP-21062. On the ADSP-21061, only channels 6-7 are available. These DMA channels allow efficient data transfers between the ADSP-2106x’s internal memory and external memory or devices.
Page 215 widths. The packing mode is selected by the PMODE bits in the DMACx control register for each external port buffer. PMODE Packing Mode No packing/unpacking 16-bit external bus to/from 32-bit internal packing 16-bit external bus to/from 48-bit internal packing 32-bit external bus to/from 48-bit internal packing The external port buffer can pack data most significant word (MSW) first or least significant word (LSW) first.
Page 216: Packing Status
6 DMA 40-bit extended precision data may be transferred using the 48-bit packing mode. Refer to the Memory chapter of this manual for a description of memory allocation for different word widths. 6.4.1.2 Packing Status Each external port DMA control register also contains a two-bit PS field which contains the number of short words currently packed in the EPBx buffer.
Page 217 in the following manner: M H E DMA Mode of Operation Slave Mode. The DMA request is generated whenever the receive buffer is not empty or the transmit buffer is not full. Reserved Handshake Mode. (For the ADSP-21060 and ADSP-21062, applies to EPB1, EPB2 buffers, channels 7, 8 only.
Page 218: Master Mode
6 DMA 6.4.3.1 Master Mode When the DMACx bits are set such that MASTER=1, HANDSHAKE=0, and EXTERN=0, then the corresponding DMA channel operates in master mode. This means that the ADSP-2106x’s DMA controller will generate internal DMA requests for that channel until the DMA sequence is completed.
Page 219 EPBx buffer has valid data. The EI, EM, and EC registers are not used in slave mode DMA. External to Internal To explore the operation of slave mode DMA, consider the case where an external device wishes to transfer a block of data into the ADSP- 2106x’s internal memory.
Page 220: Handshake Mode
6 DMA 0) in the SYSCON register. Note that ACK (or REDY) is only deasserted during a write when the EPBx FIFO buffer is full. ACK (or REDY) remains asserted at the end of a completed block transfer if the EPBx buffer is not full. When reading, the buffer will be empty at the end of the block transfer and ACK (or REDY) will be deasserted if an additional read is attempted.
Page 221 Handshake mode DMA is enabled when the HSHAKE bit is set to 1 in the corresponding DMACx control register (DMAC7 or DMAC8 on an ADSP-21060 or ADSP-21062; DMAC7 or DMAC6 on an ADSP-21061). If the MASTER bit is 0, the ADSP-2106x handshakes by returning DMAGx .
Page 222 6 DMA The DMA controller has a three-cycle pipeline, similar to the fetch–decode–execute pipeline of the core processor’s program sequencer. The DMA request and arbitration occur in the fetch cycle. The DMA address generation and bus arbitration occur in the decode cycle and the data transfer occurs in the execute cycle.
Page 223: Figure 6.8 Dma Handshake Timing With Asynchronous Requests
DMAG has a wait state DMAR rising because DMAR remained edge allows 1st asserted in the cycle prior DMAG to complete to the DMAG assertion 1st DMA 2nd DMA Request request DMARx DMAGx data DATA data valid data valid 47-0 data valid valid Transition...
Page 224: External Handshake Mode
6 DMA The ADSP-2106x will not begin external bus arbitration in response to DMARx if the EPBx buffer is full during a write or empty during a read. This is a blocked condition. Bus arbitration will begin when the EPBx buffer is serviced by the DMA controller and the full or empty state changes (i.e.
Page 225: System Configurations For Adsp-2106X Interprocessor Dma
DMARx input must be kept high during this instruction DMARx (DMARx ignored) (DMARx ignored) Enable DMA by setting Instruction DEN=1 and HSHAKE=1 executing in DMAC7 or DMAC8 control register(s) DMAR DMAR Figure 6.9 x Delay After Enabling Handshake DMA the ADSP-2106x core had requested it. The ADSP-2106x’s EPBx buffers do not latch or drive any data, however, and no internal memory DMA transfers are performed.
Page 226: Dma Throughput
6 DMA DMAGx If the external device is writing data to the latch, the signal is used as the output enable signal for the latch. If the external device is DMAGx reading from the latch, is used to clock the data on its rising DMARx edge.
Page 227: Figure 6.10 System Configurations For Adsp-2106X-To-Adsp-2106X Dma
ADSP-2106x ADSP-2106x Configuration Configuration Throughput Advantages, (Data Source) (Data Destination) (cycles/transfer) Disadvantages Bus Master Bus Slave Advantage: Destination automatically generates DMA Master Mode (MASTER=1) DMA Slave Mode (MASTER=0) interrupt upon completion. TRAN=1 TRAN=0 EIx = address of EPBx buffer Disadvantage: DMA must be programmed on in destination both source and destination.
Page 228: Figure 6.11 Example Dma Hardware Interface
6 DMA ADSP-2106x Latch 16, 32, or 48 DMA Data Bus BR BR 2 2 ADDR ADDR 31-0 31-0 BR BR 1 1 BR BR 3-6 DATA DATA 47-0 47-0 ID ID 2-0 DMAR1 DMAR1 DMA Read Request DMAG1 DMAG1 DMA Read Grant DMAR2 DMAR2...
Page 229 CLKIN fetch/decode cycles — two cycles minimum DMAR DMAG DATA valid 47-0 DMAR DMARx/ x/DMAG DMAGx x Figure 6.12 Timing Notes: DMAR – x setup times relate to the use of the signal in that cycle by the ADSP-2106x. DMA requests may be asserted asynchronously to CLKIN. DMAG DMAG –...
Page 230: Two-Dimensional Dma
6 DMA TWO-DIMENSIONAL DMA This section describes the changes in functionality that occur when the ADSP-21060 or ADSP-21062 is placed in two-dimensional DMA mode. (Note that two-dimensional DMA mode does not apply to the ADSP- 21061.) 2-D DMA mode is enabled by the L2DDMA bit in the LCOM control register and the D2DMA bit in the SRCTL0 and SRCTL1 registers.
Page 231: D Dma Operation
elements in the X dimension. This is used to reload the X count register when it decrements to zero. The X Count register (C) contains the number of data elements left in the current row. This initially has the same value as X initial count.
Page 232 6 DMA Second cycle: • The X Count is restored into the C register from the DA register. • The Y Increment value in the DB register is added to the current address in II. • The Y Count in GP is decremented. •...
Page 233: Overview
Multiprocessing OVERVIEW The ADSP-2106x includes functionality and features that allow the design of multiprocessing DSP systems. These features include distributed on-chip arbitration for bus mastership and multiprocessor accesses of the internal memory and IOP registers of other ADSP-2106xs. The ADSP-2106x also has the ability to lock the bus in order to perform indivisible read-modify-write sequences for semaphores.
Page 234: Figure 7.1 Adsp-2106X Multiprocessor System
7 Multiprocessing ADSP-2106x #6 ADSP-2106x #5 ADSP-2106x #4 ADSP-2106x #3 ADSP-2106x CLKIN CLKIN ADDR R 31-0 31-0 DATA DATA 47-0 RESET RESET 47-0 MEMORY CONTROL RPBA RPBA BR BR 1 1 BR BR 3-6 3-6 BR BR 2 2 ID ID 2-0 2-0 HOST INTERFACE ADSP-2106x...
Page 235 Multiprocessing The following terms are used throughout this chapter, and are defined below for reference: external bus DATA 47-0 , ADDR 31-0 , 3-0 , SBTS ADRCLK, PAGE, , ACK, and signals multiprocessor system a system with multiple ADSP-2106xs, with or without a host processor;...
Page 236: Multiprocessing System Architectures
In the other, nodes communicate through a single shared global memory via a parallel bus. The ADSP-2106x SHARC supports the implementation of point-to- point communication through its six link ports. It also supports an enhanced version of shared parallel bus communication called cluster multiprocessing.
Page 237: Cluster Multiprocessing
Multiprocessing The ADSP-2106x SHARC is ideally suited for data flow multiprocessing applications because it eliminates the need for interprocessor data FIFOs and external memory. The internal memory of the SHARC is usually large enough to contain both code and data for most applications using this topology.
Page 238 7 Multiprocessing Cluster multiprocessing systems include multiple SHARC processors connected by a parallel bus that allows interprocessor access of on-chip memory as well as access to shared global memory. In a typical cluster of SHARCs, up to six processors and a host can arbitrate for the bus. The on-chip bus arbitration logic allows these processors to share the common bus.
Page 239: Link Port Data Transfers In A Cluster
Multiprocessing Communication between processors is also facilitated by the ability of a processor to broadcast a write to all processors simultaneously. This can be used to implement reflective semaphores, where a processor polls its own internal copy of the semaphore and only uses the external bus for a broadcast write to all other processors when it wants to change it.
Page 240: Simd Multiprocessing
7 Multiprocessing 7.2.3 SIMD Multiprocessing For certain classes of applications such as radar imaging, a SIMD array may be the most efficient topology to coordinate a large number of processors in a single system. The SIMD array of Figure 7.3 consists of multiple SHARCs connected in a 2-D or 3-D mesh.
Page 241: Multiprocessor Bus Arbitration
Multiprocessing MULTIPROCESSOR BUS ARBITRATION Multiple ADSP-2106xs can share the external bus with no additional arbitration circuitry. Arbitration logic is included on-chip to allow the connection of up to six ADSP-2106xs and a host processor. Bus arbitration is accomplished with the use of the –...
Page 242: Bus Arbitration Protocol
7 Multiprocessing The ID pins provide a unique identity for each ADSP-2106x in a multiprocessing system. The first ADSP-2106x should be assigned ID=001, the second should be assigned ID=010, and so on. One of the ADSP-2106xs must be assigned ID=001 in order for the bus synchronization scheme to function properly.
Page 243 Multiprocessing The cycle in which mastership of the bus is passed from one ADSP-2106x to another is called a bus transition cycle. A bus transition cycle occurs when the current bus master’s x pin is deasserted and one of the slave’s x pins is asserted.
Page 244: Figure 7.5 Bus Arbitration Timing
7 Multiprocessing The following steps summarize the actions a slave takes to acquire bus mastership and perform an external read or write over the bus (see Figure 7.6): 1. The slave determines that it is executing an instruction which requires an off-chip access. It asserts its x line at the beginning of the cycle.
Page 245: Figure 7.6 Bus Request & Read/Write Timing
Multiprocessing 3. At the end of the bus transition cycle the current bus master releases the bus and the new bus master starts driving. Whenever the bus master stops using the bus its x line is deasserted, allowing other ADSP-2106xs to arbitrate for mastership if they need it. If no other ADSP-2106xs are asserting their x line when the master deasserts his, the master retains control of the bus and continues to...
Page 246: Bus Arbitration Priority (Rpba)
7 Multiprocessing While a slave waits to be a master for a DMA transfer, it asserts x. If that slave’s core accesses the DA group regsiters, the x will be deasserted during that access.. 7.3.2 Bus Arbitration Priority (RPBA) Two different priority schemes are available to resolve competing bus requests, fixed and rotating.
Page 247: Bus Mastership Timeout
Multiprocessing 7.3.3 Bus Mastership Timeout In either bus arbitration priority scheme, it may be desirable to limit how long a bus master can own the bus. This is accomplished by forcing the bus master to deassert its x line after a specified number of cycles, giving the other processors a chance to acquire bus mastership.
Page 248: Core Priority Access
7 Multiprocessing 7.3.4 Core Priority Access The Core Priority Access signal, , allows external bus accesses by the core processor of a slave ADSP-2106x to take priority over ongoing DMA transfers. Normally when external port DMA transfers are in progress, the core processors of the slave ADSP-2106xs cannot use the external bus until the DMA transfer is finished.
Page 249 Multiprocessing In the cycle after has been asserted, only the ADSP-2106x cores with a pending external access have their bus requests asserted. Bus arbitration now proceeds as usual, with the highest priority device becoming the master (when the previous bus master releases its line).
Page 250: Figure 7.7 Core Priority Access Timing
7 Multiprocessing When is released, all ADSP-2106xs resume normal x assertion one cycle after is sampled as high. After releasing its , the bus master will ignore the pin for two cycles. This reduces the possibility of the bus master unnecessarily losing bus mastership while the signal is pulled high by the common pullup resistors.
Page 251: Bus Synchronization After Reset
Multiprocessing 7.3.5 Bus Synchronization After Reset RESET When a multiprocessing system is reset by the pin, the bus arbitration logic on each processor must synchronize to insure that only one ADSP-2106x will drive the external bus. One ADSP-2106x must become the bus master, and all other processors must recognize which one it is before actively arbitrating for the bus.
Page 252 7 Multiprocessing When an ADSP-2106x has synchronized itself, it sets the BSYN bit in the SYSTAT register. If one ADSP-2106x comes out of reset after the others have synchronized and started program execution, that processor may not be able to synchronize immediately (e.g. if it sees more than one line asserted).
Page 253: Slave Direct Reads & Writes
Multiprocessing Although the bus synchronization scheme allows individual processors to be reset, the ADSP-2106x with ID=001 may fail to drive the memory control signals if it is in reset while any other processors are asserting their x line. If the ADSP-2106x with ID=001 has asserted while it is in reset, it RESET will be synchronized when...
Page 254: Direct Writes
7 Multiprocessing For heavily loaded buses, or when external data buffers are used, a single wait state can be added to all multiprocessor memory accesses. This option is selected by the MMSWS bit of the WAIT register. 7.4.1 Direct Writes When a direct write to a slave ADSP-2106x occurs, the address and data are latched on-chip by the I/O processor.
Page 255: Direct Reads
Multiprocessing The DWPD (Direct Write Pending) bit of the SYSTAT register indicates when a direct write to internal memory is pending in the I/O processor’s direct write FIFO or data is pending in the slave write FIFO (at the external port I/O pins). Direct writes and IOP register accesses may be completed in different sequences.
Page 256: Figure 7.8 Broadcast Write Timing Example
7 Multiprocessing Figure 7.8 shows the timing for a typical broadcast write for MMSWS=0. In this example, the first broadcast write completes without a wait state. In the second broadcast write, one or more of the slaves have 3 wait states and are deasserting ACK for 3 cycles. Note that ACK is sampled by the master on odd cycles (wrt asserted).
Page 257: Shadow Write Fifo
Multiprocessing 2. During all succeeding even cycles in which the broadcast write is not finished, the slave ADSP-2106xs will not drive ACK. Instead, the master ADSP-2106x drives (i.e. pre-charges) ACK high and must continue the write. (Go to Step 1.) In most cases the ACK signal will be high and the ADSP-2106x slaves will be ready to accept data at the start of the broadcast write—the write completes in one cycle.
Page 258: Data Transfers Through The Epbx Buffers
7 Multiprocessing If 48-bit accesses and 32-bit accesses to the same locations absolutely must be mixed in this way, you must flush out the shadow FIFO with two dummy writes before attempting to read the data. DATA TRANSFERS THROUGH THE EPBx BUFFERS In addition to direct reads and writes, the ADSP-2106x bus master can transfer data to and from the slave ADSP-2106xs through the external port FIFO buffers, EPB0, EPB1, EPB2, and EPB3.
Page 259: Interrupts For Single-Word Transfers
Multiprocessing Similarly, if the ADSP-2106x master attempts a write to a full EPBx buffer on a slave, the access will be held off with ACK until the buffer is read by the slave’s core. If the slave’s core attempts to read from an empty buffer, the access is also held off and the core will hang until the buffer is externally written from the bus master.
Page 260: Dma Transfers
7 Multiprocessing 7.5.2 DMA Transfers The ADSP-2106x bus master can also set up DMA transfers to and from a slave ADSP-2106x. The master can write to the slave’s DMA control and parameter registers to set up an external port DMA operation.
Page 261: Dma Transfers To External Memory
Multiprocessing 7.5.2.2 DMA Transfers To External Memory The ADSP-2106x’s DMA controller can also be used to transfer data directly to external memory. The external handshake mode for external DMAR DMAG port DMA channel 7 or 8 will provide the handshaking for this type of transfer. Again, this is not possible when a host processor has gained control of the bus.
Page 262 7 Multiprocessing Bus lock is requested by setting the BUSLK bit in the MODE2 register. When this happens, the ADSP-2106x initiates the bus arbitration process in the usual fashion, by asserting its x line. When it becomes bus master, it locks the bus (i.e. retains bus mastership) by keeping its x line asserted even when it is not performing an external read or write.
Page 263: Example: Sharing A Dma Channel With Reflective Semaphores
Multiprocessing 7.6.1 Example: Sharing A DMA Channel With Reflective Semaphores A single DMA channel can be shared by more than one ADSP-2106x by using the channel’s control register as a reflective semaphore. The DMA channel control register is a memory-mapped IOP register on each ADSP-2106x.
Page 264: Interprocessor Messages & Vector Interrupts
7 Multiprocessing INTERPROCESSOR MESSAGES & VECTOR INTERRUPTS The ADSP-2106x bus master can communicate with slave ADSP-2106xs by writing messages to their IOP registers. The MSGR0-MSGR7 registers are general-purpose registers which can be used for convenient message passing between ADSP-2106xs. They are also useful for semaphores and resource sharing between multiple ADSP-2106xs.
Page 265: Vector Interrupts (Virpt)
Multiprocessing the master sees a “0” in TH, it knows that the transfer is complete. A similar sequence of events occurs when the slave passes data to the master through R and RH. The register write-back method is similar to register handshaking, but uses only the T and R data registers.
Page 266: Systat Register Status Bits
7 Multiprocessing The DWPD (Direct Write Pending) bit of the SYSTAT register indicates when a direct write to internal memory is pending. Pending direct writes may occur in different sequences. If, for example, the master ADSP-2106x performs a direct write to a slave and then writes to an IOP register on the slave, the IOP register write may complete before the direct write.
Page 267: Figure 7.9 Systat Register
Multiprocessing HSTM Host Mastership BSYN Bus Synchronization CRBM Current Bus Master ID Code DWPD Direct Write Pending VIPD Vector Interrupt Pending Host Packing Status 00 = packing complete 01 = first stage of all packing and unpacking modes 10 = second stage of 16-to-48 bit packing/unpacking or 32-to-48 bit packing/unpacking Figure 7.9 SYSTAT Register 7 –...
Page 268 7 Multiprocessing HSTM Host Mastership. Indicates whether the host processor is has been granted control of the bus. 1=Host is bus master 0=Host is not bus master BSYN Bus Synchronization. Indicates when the ADSP-2106x’s bus arbitration logic is synchronized after reset. (See “Bus Synchronization After Reset.”) 1=Bus arbitration logic is synchronized 0=Bus arbitration logic is not synchronized Current Bus Master.
Page 269: Overview
Host Interface OVERVIEW The ADSP-2106x’s host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit, with little additional hardware required. The ADSP-2106x accommodates either synchronous or asynchronous data transfers, allowing the host to use a different clock frequency. Asynchronous transfers at speeds up to the full clock rate of the processor are supported.
Page 270: Figure 8.1 External Port & Host Interface
8 Host Interface Any host microprocessor with a standard memory interface can easily connect to the ADSP-2106x bus through buffers. By providing an address, a data bus, and memory control signals—i.e. read, write and chip select—a host may access any device on the ADSP-2106x bus as if it were a memory.
Page 271: Table 8.1 Host Interface Signals
Host Interface Table 8.1 defines the ADSP-2106x pins used in host processor interfacing. Signal Type Definition Host Bus Request. Must be asserted by a host processor to request control of the ADSP-2106x’s external bus. When is asserted in a multiprocessing system, the ADSP-2106x that is bus master will relinquish the bus and assert .
Page 272 8 Host Interface The following terms are used throughout this chapter, and are defined below for reference: external bus DATA 47-0 , ADDR 31-0 , 3-0 , SBTS ADRCLK, PAGE, , ACK, and signals multiprocessor system a system with multiple ADSP-2106xs, with or without a host processor;...
Page 273: Host Processor Control Of The Adsp-2106X
Host Interface direct reads & writes a direct access of the ADSP-2106x’s internal memory or IOP registers by another ADSP-2106x or by a host processor external port FIFO buffers EPB0, EPB1, EPB2, and EPB3—the IOP registers used for external port DMA transfers and single-word data transfers (from other ADSP-2106xs or from a host processor);...
Page 274: Acquiring The Bus
8 Host Interface 8.2.1 Acquiring The Bus For a host processor to gain access to the ADSP-2106x, it must first assert , the host bus request signal. has priority over all multiprocessor bus requests, and when asserted will cause the current ADSP-2106x master to give up the bus to the host as soon as it has finished the current bus cycle.
Page 275: Figure 8.2 Example Timing For Bus Acquisition
Host Interface HBR should not be removed before the access is complete (Asynchronous) HBG to buffer enable (Synchronous) HBG to buffer disable current bus master internal BR low wait for HBG, CS, and RD or WR REDY wait state (open drain) ADSP-2106x drive RD/WR ADSP-2106x drive...
Page 276: Asynchronous Transfers
8 Host Interface • Synchronous accesses may not be used in systems with only one ADSP-2106x (with ID =000). Once the host has finished its task, it can relinquish control of the bus by deasserting . The ADSP-2106x bus master responds by deasserting .
Page 277 Host Interface Host direct reads and writes can be performed with normal words (32-bit or 48-bit) or short words (16-bit). Short words are accessed if the S field of the address is “1m”, where “m” is the most significant bit of the short word address.
Page 278: Asynchronous Transfer Timing
8 Host Interface 8.2.2.1 Asynchronous Transfer Timing When a ADSP-2106x’s chip select is asserted (low), the selected ADSP-2106x immediately deasserts the REDY signal, with a delay of approximately 10 ns. Refer to the ADSP-2106x Data Sheet for timing exact specifications. (The REDY deassertion is activated from not from because the host interface buffers for may not yet be enabled if...
Page 279: Figure 8.3 Example Timing For Host Read & Write Cycles
Host Interface Host Driven valid address valid by Host Address Host Write Host Read Host buffers turn on Driven by Driven inactive ADSP-2106x before trisate Bus Master Driven by each REDY ADSP-2106x data setup REDY deasserted for a min of 1 cycle valid data from DATA valid...
Page 280: Synchronous Transfers
8 Host Interface Figure 8.3 also shows the timing of a host read cycle, again assuming the use of the bus interface hardware of Figure 8.8, with the following sequence: 1. The host asserts the address. and the appropriate line are again decoded by the host bus interface address comparator.
Page 281: Host Interface Deadlock Resolution With Sbts
Host Interface When performing synchronous transfers, the host should use the same number of wait states as are configured for multiprocessor memory space wait states; otherwise the system may hang. This is configured by the MMSWS bit of the WAIT register. When an ADSP-2106x is responding to a synchronous read access, it will only drive valid data for one cycle, even if the access is prolonged by the host.
Page 282: Direct Writes
8 Host Interface The host can directly read and write the IOP registers to control and configure the ADSP-2106x, for example in SYSCON and SYSTAT, and to set up DMA transfers. The IWT (Instruction Word Transfer) bit controls internal memory width for instruction transfers.
Page 283: Direct Reads
Host Interface If the buffer is full when a write is attempted, the ADSP-2106x will deassert ACK (or REDY) until the buffer is not full. The buffer will usually empty out within one cycle, thus creating a write latency, unless higher priority on-chip DMA transfers are occurring. Slave reads will be held off when there is data in the write FIFO—this prevents false data reads and out-of-sequence operations.
Page 284 8 Host Interface system; see “Bus Lock & Semaphores” in the Multiprocessing chapter of this manual. Broadcast writes can also be used to simultaneously download code or data to multiple processors. Asynchronous broadcast writes and synchronous broadcast writes are performed differently by the host. For asynchronous broadcast writes, the host must assert on each ADSP-2106x that it wants to write to.
Page 285: Shadow Write Fifo
Host Interface In most cases the ACK signal will be high and the ADSP-2106x slaves will be ready to accept data at the start of the synchronous broadcast write—the write completes in one cycle. If the ACK signal is low, however, or one of the slaves is not ready to accept the data, the write will take a minimum of three cycles.
Page 286: Data Transfers Through The Epbx Buffers
8 Host Interface DATA TRANSFERS THROUGH THE EPBx BUFFERS In addition to direct reads and writes, the host processor can transfer data to and from the ADSP-2106x through the external port FIFO buffers, EPB0, EPB1, EPB2, and EPB3. Each of these buffers, which are part of the IOP register set, is a six-location FIFO.
Page 287: Interrupts For Single-Word Transfers
Host Interface Each EPBx buffer can be flushed (i.e. cleared) by writing a 1 to the FLSH bit in the corresponding DMACx control register. This bit is not latched internally and will always be read as a 0. Status can change in the following cycle.
Page 288: Dma Transfers
8 Host Interface 8.4.2 DMA Transfers The host processor can also set up DMA transfers to and from the ADSP-2106x. Once the host has gained control of the ADSP-2106x, it can access the on-chip DMA control and parameter registers to set up an external port DMA operation.
Page 289: Dma Transfers To External Memory
Host Interface 8.4.2.2 DMA Transfers To External Memory The ADSP-2106x’s DMA controller can also be used to transfer data directly from the host to external memory. The external handshake mode DMAR for external port DMA channel 7 or 8 will provide the DMAG x handshaking for this type of transfer.
Page 290: Figure 8.4 Syscon Register
8 Host Interface 30 29 25 24 IMGR EBPR Internal Memory Grouping External Bus Priority (for mesh multiprocessing) 00=even, 01=core processor, 10=I/O processor DCPR DMA Channel 6-9 Priority 1 = rotating, 0 = sequential 15 14 SRST Software Reset MSIZE External Memory Bank Size Boot Select Override MSIZE = log 2 (bank size) –...
Page 291 Host Interface Host Packing Mode. Specifies the internal word width and external host bus width for host processor accesses of the ADSP-2106x’s internal memory or IOP registers. If the host access is a read or write of any IOP register other than the external port FIFO buffers (EPB0-EPB3) or link port buffers (LBUF0-LBUF5), the word width will always be 32 bits no matter what the host bus width is.
Page 292 8 Host Interface IMDWx Internal Memory Block Data Width. Selects the data word width for each block of internal memory. For 32-bit data words, set IMDWx to 0. For 40-bit data (transferred within 48-bit words), set IMDWx to 1. IMDW0 (bit 8 of SYSCON) selects the data word width for memory block 0 and IMDW1 (bit 9) selects the data word width for memory block 1.
Page 293: Data Bus Lines Used For Different Packing Modes
Host Interface During packed transfers with a slow host, the host may relinquish the bus before the current word has been fully packed—the bus may be released after the first part of the word is written and then, some time later, reasserted and the second part of the word written.
Page 294: Bit Data Packing
8 Host Interface Figure 8.a shows how different data word sizes are transferred over the external port. DATA 47-0 EPROM Boot 16-Bit Packed 32-Bit Float or Fixed, D31 - D0, 32-Bit Packed 40-Bit Extended Float Instruction Fetch Figure 8.a External Port Data Alignment 8.5.3 32-Bit Data Packing For a 16-bit host bus, the incoming data is latched on DATA...
Page 295: Figure 8.5 Example Timing For Host Interface Data Packing
Host Interface 16/32 Bit Packing Host Address (15:1) Write Address Read Address (Same) Read Address (Same) Write Address REDY write 1st word write 2nd word read 1st word read 2nd word into ADSP-2106x into ADSP-2106x from ADSP-2106x from ADSP-2106x valid valid valid DATA...
Page 296: Bit Instruction Packing
8 Host Interface • The host initiates another read access, driving the address of the data to be accessed and then asserting • The ADSP-2106x transmits the 2nd 16-bit word. When a host writes a 32-bit word with 16-bit packing, again using the typical bus interface hardware shown in Figure 8.8, the following sequence of events occurs (also illustrated in Figure 8.5): •...
Page 297: Systat Register Status Bits
Host Interface 32-Bit to 48-Bit Word Packing (Host Bus ADSP-2106x): Data Bus Lines 47-32 Data Bus Lines 31-16 1st transfer Word1, bits 47-32 Word1, bits 31-16 2nd transfer Word2, bits 15-0 Word1, bits 15-0 3rd transfer Word2, bits 47-32 Word2, bits 31-16 The HMSWF bit of SYSCON is ignored for 32-to-48-bit packing.
Page 298: Figure 8.6 Systat Register
8 Host Interface 30 29 25 24 HSTM Host Mastership BSYN Bus Synchronization CRBM Current Bus Master ID Code DWPD Direct Write Pending VIPD Vector Interrupt Pending Host Packing Status 00 = packing complete 01 = first stage of all packing and unpacking modes 10 = second stage of 16-to-48 bit packing/unpacking or 32-to-48 bit packing/unpacking Figure 8.6 SYSTAT Register HSTM...
Page 299: Interprocessor Messages & Vector Interrupts
Host Interface ID Code. Indicates the ID inputs of this ADSP-2106x. DWPD Direct Write Pending. Indicates when a direct write to the ADSP-2106x’s internal memory is pending. The DWPD bit is cleared when the direct write has been completed. (Direct writes may be delayed for several cycles if DMA chaining is underway or if higher priority DMA requests occur.
Page 300: Message Passing (Msgrx)
8 Host Interface • Vector Interrupts. The host can issue a vector interrupt to the ADSP-2106x by writing the address of an interrupt service routine to the VIRPT register. This causes an immediate high-priority interrupt on the ADSP-2106x which, when serviced, will cause the ADSP-2106x to branch to the specified service routine.
Page 301: Host Vector Interrupts (Virpt)
Host Interface 8.7.2 Host Vector Interrupts (VIRPT) Vector interrupts are used for interprocessor commands between the host and an ADSP-2106x or between two ADSP-2106xs. When the external processor writes an address to the ADSP-2106x’s VIRPT register a vector interrupt is caused. When the vector interrupt is serviced, the ADSP-2106x automatically pushes the status stack and begins executing the service routine located at the address specified in VIRPT.
Page 302: System Bus Interfacing
8 Host Interface write may complete before the direct write. Because of this, direct writes performed just before vector interrupt writes (to VIRPT) may be delayed until after the branch to the interrupt vector: 1. The host processor performs a direct write to the internal memory of an ADSP-2106x.
Page 303: Figure 8.7 Basic System Bus Interface
Host Interface System Bus Interface ADSP-2106x BR BR 2 2 ADDR ADDR 31-0 31-0 System Data Bus BR BR 1 1 BR BR 3-6 DATA DATA 47-0 47-0 T/ T/R R ID ID 2-0 Write REDY REDY Read MS 3-0 REDY REDY REDY...
Page 304: Access To The System Bus—Master Adsp-2106X
8 Host Interface 8.8.2 Access To The System Bus—Master ADSP-2106x Figure 8.8 shows a more complex, bidirectional system interface in which the ADSP-2106x subsystem can access the system bus by becoming a bus master. Before it begins the access, the ADSP-2106x must first request permission to become the bus master by generating the System Bus Request signal ( ).
Page 305: Figure 8.8 Bidirectional System Bus Interface
Host Interface System Bus Interface ADSP-2106x System Data Bus BR BR 2 2 ADDR ADDR 31-0 31-0 BR BR 1 1 BR BR 3-6 DATA DATA 47-0 47-0 ID ID 2-0 FLAG0 FLAG0 SBTS SBTS Host Write REDY REDY MS 3-0 Host Read REDY REDY...
Page 306: Deadlock Resolution
8 Host Interface 8.8.2.2 Deadlock Resolution In the rare case where both the ADSP-2106x subsystem and the system are trying to access each other’s bus in the same cycle, a deadlock may occur in which neither access can complete; ACK stays deasserted. Normally the master ADSP-2106x will respond to an request by asserting...
Page 307: Adsp-2106X Dma Access To System Bus
Host Interface 4. The host deasserts will be deasserted when the internal read buffer is empty. 5. One cycle after the ADSP-2106x deasserts , the ADSP-2106x restarts its suspended access. 8.8.2.3 ADSP-2106x DMA Access To System Bus SBTS The use of the inputs to resolve a system bus deadlock, as described above, cannot be used for DMA transfers because once a DMA word transfer has begun in the ADSP-2106x, it must be...
Page 308: Multiprocessing With Local Memory
8 Host Interface 8.8.3 Multiprocessing With Local Memory Figure 8.9 shows how several ADSP-2106x subsystems may be connected together on a system bus for high throughput. The gate array implements bus arbitration when the system bus is accessed. The buffers isolate the ADSP-2106x local buses from the system bus. This example system works in the following way: •...
Page 309: Adsp-2106X To Microprocessor Interface
Host Interface System Bus Address SYSTEM BUS ADSP-2106x Group Local Bus ADDR ADDR Buffer DATA DATA ENABLE Local Memory SBTS SBTS System Memory System Arbitration DATA DATA (Gate Array) ADDR ADDR System Bus Address ADSP-2106x Group Local Bus ENABLE ADDR ADDR 31-0 31-0 Buffer...
Page 310 8 Host Interface 8 – 42 www.BDTIC.com/ADI...
Page 311: Overview
Link Ports OVERVIEW The ADSP-2106x SHARC provides additional I/O capability through six dedicated 4-bit link ports. Each link port consists of four bidirectional data lines, a bidirectional clock line, and a bidirectional acknowledge line. The link ports can be clocked twice per processor clock cycle, allowing each port to transfer up to 8 bits of data per cycle.
Page 312: Link Port To Link Buffer Assignment
9 Link Ports The six pins associated with each link port are listed in Table 9.1. Each link port consists of four bidirectional data lines, LxDAT , and two handshake lines, Link Clock (LxCLK) and Link Acknowledge (LxACK). The LxCLK line allows asynchronous data transfers and the LxACK line provides handshaking.
Page 313: Figure 9.B Link Port Communication Examples
Link Ports Link Link Link ADSP-2106x ADSP-2106x ADSP-2106x Ports Ports Ports ADSP-2106x ADSP-2106x ADSP-2106x Link Link Link Ports Ports Ports External External External Port Port Port Dataflow SHARC Cluster ADSP-2106x ADSP-2106x ADSP-2106x Link Link Link Link Link Link Ports Ports Ports Ports Ports...
Page 314: Link Port Dma Channels
9 Link Ports 9.1.2 Link Port DMA Channels Link buffers 0-5 are supported by DMA channels 1, 3, 4, 5, 6, and 7 respectively: DMA Channel 1 Link Buffer 0 (shared with SPORT1 Receive) DMA Channel 3 Link Buffer 1 (shared with SPORT1 Transmit) DMA Channel 4 Link Buffer 2 DMA Channel 5...
Page 315: Link Port Interrupts
Link Ports 9.1.3 Link Port Interrupts Three types of interrupts are dedicated to the link ports: • If DMA is enabled, a maskable interrupt is generated when the DMA block transfer has completed. • If DMA is disabled, then the link buffer may be read or written by the core processor as a memory-mapped location (part of the IOP register space).
Page 316: Link Buffer Control Register (Lctl)
9 Link Ports 9.2.1 Link Buffer Control Register (LCTL) The LCTL register contains control bits unique to each link buffer. Table 9.2 describes the control bits in LCTL. Bit(s) Name Definition Link buffer 0 controls Link buffer 1 controls 8-11 Link buffer 2 controls 12-15 Link buffer 3 controls...
Page 317 Link Ports LEXTx Specifies word size for each link buffer: LEXTx=1 specifies 48-bit transfers in link buffer x LEXTx=0 specifies 32-bit transfers in link buffer x Link buffer data is transmitted and received MSB-first. LEXTx must not be changed while that link buffer is enabled, as this will cause the nibble packing to initialize to an incorrect value.
Page 318: Figure 9.2 Lctl Register
9 Link Ports 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LEXT5 LBUF5 Extended Word Size L4EN 1=48-bit transfers LBUF4 Enable 0=32-bit transfers L4DEN LEXT4 LBUF4 DMA Enable LBUF4 Extended Word Size L4CHEN 1=48-bit transfers LBUF4 Chained DMA Enable...
Page 319: Link Common Control Register (Lcom)
Link Ports 9.2.2 Link Common Control Register (LCOM) The LCOM register contains status bits, packing status bits, and 2X clock rate bits for each buffer. These bits are listed in Table 9.3. Bit(s) Name Definition L0STAT(0:1) Link buffer 0 status: 11=full, 00=empty,10=one word * L1STAT(0:1) Link buffer 1 status: 11=full, 00=empty,10=one word * L2STAT(0:1)
Page 320 9 Link Ports LCOM Control Bits: LxSTAT(0:1) When transmitting, these status bits indicate whether there is room in the buffer for more data. When receiving, these status bits indicate whether new (unread) data is available in the receive buffer. LxSTAT(1)=1 if there is data in the buffer. LxSTAT(0)=0 if there is room in the buffer.
Page 321: Figure 9.3 Lcom Register
Link Ports 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 LRERR5 LCLKX24 Rcv. Pack Error Status for Link Buffer 5 Transfer at 2x Clock Rate 1=incomplete, 0=complete on Link Buffer 4 LRERR4 LCLKX25 Rcv.
Page 322: Link Assignment Register (Lar)
9 Link Ports 9.2.3 Link Assignment Register (LAR) Each link port is assigned to a link buffer by a 3-bit group in the Link Assignment Register (LAR). There are 6 such groups, one for each buffer, as shown in Table 9.4. The LAR can be thought of as performing a logical (i.e.
Page 323: Handshake Control Signals
Link Ports 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 A5LB A0LB Link Port Assigned to LBUF5 Link Port Assigned to LBUF0 A4LB A1LB Link Port Assigned to LBUF4 Link Port Assigned to LBUF1 A3LB A2LB...
Page 324: Figure 9.5 Link Port Handshake Timing
9 Link Ports LCLK stays high at nibble 0 if LACK is sampled low on previous LCLK rising edge LCLK Minimum LACK Note: LCLK high indicates a stall set-up time LACK LACK will reassert LACK may deassert Transmitter samples LACK as soon as the link after the second here to determine whether...
Page 325: Link Buffers
Link Ports To allow a transmitter and a receiver to be enabled (assigned and link buffer enabled) at different times, LxACK, LxCLK, and LxDAT be held low with the 50 kΩ internal pulldown resistors if LPDRD is cleared when the link port is disabled. Thus, if the transmitter is enabled before the receiver, LxACK will be low and the transmission is held off.
Page 326: Core Processor Access To Link Buffers
9 Link Ports 9.4.1 Core Processor Access To Link Buffers In applications where the latency of link port DMA transfers to and from internal memory is too long, or where a process is continuous and has no block boundaries, the ADSP-2106x processor core may read or write link buffers directly using the full/empty status bit of the link buffer to automatically pace the operation.
Page 327 Link Ports DMA Channels 1 and 3 are shared by link buffers 0 and 1, respectively, and by SPORT1. This has several functional implications: • If the SPORT1 receive DMA enable bit or chaining enable bit is set, then SPORT1 receive is assigned DMA channel 1. •...
Page 328: Dma Chaining For Link Ports
9 Link Ports 9.5.1 DMA Chaining For Link Ports In chained DMA operations, the ADSP-2106x automatically sets up another DMA transfer when the contents of the current buffer have been transmitted (or received). The chain pointer register (CPx) is used to point to the next set of buffer parameters stored in memory.
Page 329: Link Port Interrupts With Dma Enabled
Link Ports If the DMA is disabled but the associated link buffer is enabled, then a maskable interrupt is generated whenever a receive buffer is not empty or when a transmit buffer is not full. The interrupt latch bit in IRPTL may be masked in the corresponding IMASK register bit.
Page 330: Figure 9.5A Logic For Link Port Interrupts
9 Link Ports being latched in the LSRQ register. The six possible receive LSRs and the six possible transmit LSRs are ORed together to generate the link service request interrupt. The LSRQ interrupt request may be masked by the LSRQI mask bit of the IMASK register. When the mask bit is set, the interrupt is allowed to pass into the interrupt priority encoder.
Page 331: Table 9.5 Link Service Request Register (Lsrq)
Link Ports This need for masking is due to a delay before LxCLK or LxACK (if already asserted) signals are pulled (if pulldowns enabled) or driven externally (if pulldowns disabled) below logic threshold. During this delay, these signals are sampled asserted and generate an LSRQ. To avoid the possiblity of spurious interrupts, mask the LSRQ interrupt or the appropriate request bit in the LSRQ register and allow an appropriate delay before unmasking.
Page 332: Figure 9.6 Lsrq Register
9 Link Ports 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 L5RRQ L0TRQ Link Port 5 Receive Request Link Port 0 Transmit Request L5TRQ L0RRQ Link Port 5 Transmit Request Link Port 0 Receive Request L4RRQ L1TRQ Link Port 4 Receive Request...
Page 333: Transmission Error Detection
Link Ports TRANSMISSION ERROR DETECTION Transmission errors on the link ports may be detected by reading the LRERRx bits in the LCOM register. These bits reflects the status of each nibble counter. The LRERRx bit will be zero if the pack counter of the corresponding link buffer is zero (i.e.
Page 334: Figure 9.7 Token Passing Flow Chart
9 Link Ports Original Master Original Slave • DMA transfer complete • DMA transfer complete • LBUF disabled • LBUF disabled • LSRQ interrupt enabled • LBUF RX non-DMA enabled • LACK assertion causes LSRQ interrupt • LBUF TX non-DMA enabled •...
Page 335 Link Ports If the master wishes to give up the token, he may send back a user- defined token release word and thereafter clear his token flag. Simultaneously, the slave examines the data sent back and if it is the token release word, the slave will set his token, and can thereafter transmit.
Page 336: Link Transmission Lines
9 Link Ports • Ensure that the link interrupt selection matches the application. If a status detection scheme using the status bits of the LSRQ register is to be used, it is important to note the following: If a link port that is configured to receive is disabled while LxACK is asserted, there will be an RC delay before the 50k ohm pulldown resistor on LxACK (if enabled) can pull the value below logic threshold.
Page 337: System Design Example: Local Dram Interface
Link Ports 9.10 SYSTEM DESIGN EXAMPLE: LOCAL DRAM INTERFACE The example shown in Figure 9.8 shows how a multiprocessing system can use link ports to connect to local memories and I/O devices. An ASIC implements the interface between the link port and DRAM or an I/O device.
Page 338: Programming Examples
9 Link Ports 9.11 PROGRAMMING EXAMPLES Listings 9.1 and 9.2 illustrate two ways to perform link port data transfers. 9.11.1 Core-Driven Single-Word Transfers Listing 9.1 shows an example of single-word data transfers controlled by the ADSP-2106x core. 9.11.2 DMA Transfers Listing 9.2 shows an example DMA transfer program.
Page 339 Link Ports /*_______________________________________________________________ ADSP-2106x DMA-Driven LINK Loopback Example This example shows an internally looped-back link port transfer. Two DMA channels are used. Link buffer 3 (LBUF3) and corresponding DMA channel 5 is used for transmit. Link buffer 2 (LBUF2) and corresponding DMA channel 5 is used for receive.
Page 340: Listing 9.2 Dma Transfer Example
9 Link Ports r0=0x0003f03f; /* LAR Register: LBUF2->Port0, LBUF3->Port0 */ dm(LAR)=r0; /* All others inactive. r0=0x0000b300; /* LCTL Register: 32-bit data, LBUF2=rx, LBUF3=tx */ dm(LCTL)=r0; /* Enable DMA on LBUF2 and LBUF3. /* This will start off the DMA transfer. /* Always write LCTL after LAR.
Page 341: Listing 9.3 Link Token Passing Example
Link Ports /*_____________________________________________________________________________ ADSP-2106x LINK Token Pass Example This is an example of software protocol for token ring passing through the link ports using LSRQ. This code is to be loaded on both the original master and the original slave. The code is ID intelligent for multiprocessor systems: ID1 is the original master (transmitter) and ID2 is original slave (receiver).
Page 342 9 Link Ports .var source_3[N]= 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888; .var destination_1[N]; .var destination_2[N]; .var destination_3; .ENDSEG; .SEGMENT/PM isr_tabl; /* Interrupt Service Table NOP; NOP;NOP;NOP; /* Reserved interrupt rst_svc: nop; jump start; nop; nop; NOP; NOP; NOP; NOP; sovfi_svc: RTI;...
Page 343 Link Ports /*____________________main routine____________________*/ .SEGMENT/PM pm_code; start: bit set mode2 FLG0O; /* Set Flag0 for output bit clr astat FLG0; /* Clear Flag0 for use as flag to test /* if this SHARC is the original master r0=dm(SYSTAT); r0=FEXT r0 BY 8:3; /* Extract Processor ID from SYSTAT r1=orig_master_id;...
Page 344 9 Link Ports r0=0xc000; /* LCOM Register: 2x rate on LBUF3, dm(LCOM)=r0; /* note:use r0=0x00010000 on rev. 0.X silicon r0=0x3f1ff; /* LAR Register: LBUF3->port 0 dm(LAR)=r0; /* All others inactive bit set imask LP3I; /* Enable Link buffer 3 interrupt bit set mode1 IRPTEN;...
Page 345 Link Ports /*_______________Allow for pulldown delay on LxACK of the slave_________________*/ bit clr imask LSRQI; /* Disable Link port service request interrupt r0=0x10; dm(LSRQ)=r0; /* Unmask LSRQ lport 0 transmit request status r0=0x00000000; dm(LCTL)=r0; /* LCTL: disable all LBUFs disabled1: r0=dm(LSRQ);...
Page 346 9 Link Ports lp3_orig_slave: /* Finish by setting up Tx without DMA bit clr imask LP3I; /* disable Link buffer 2 interrupt r0=0x3f1ff; dm(LAR)=r0; /* LAR Register: LBUF3->port 0 r0=0x00009000; dm(LCTL)=r0; /* enable LBUF3 Tx, No DMA rti; /*_______________Link Service Request Interrupt Routine______________*/ lsrq: bit clr imask LP3I;...
Page 347 Link Ports r1=0xc0; /* check if slave wants the token r0=dm(LCOM); /* check if slave emptied the fifos r0=r0 AND r1; /* within 10 cycles if NE jump second_master_mode; /* else second master mode slave_mode: /*_______________Protection to avoid two transmitting link ports________________*/ bit clr imask LSRQI;...
Page 348 9 Link Ports r0=dm(LBUF2); /* read DMA size dm(C4)=r0; /* Set DMA count to length of data buffer */ r0=destination_3; dm(II4)=r0; /* Set DMA rx index to start of destin buffer r0=1; dm(IM4)=r0; /* step size r0=0x00000300; dm(LCTL)=r0; /* enable LBUF2 DMA Rx bit clr irptl LP2I;...
Page 349 Link Ports dm(IM4)=r0; /* Set DMA modify (stride) to 1 r0=@source_2; dm(C4)=r0; /* Set DMA count to length of data buffer. r0=0x00000b00; /* LCTL Register:32-bit data, LBUF2=tx dm(LCTL)=r0; /* enable DMA on LBUF2. /* This will start off the DMA transfer. /* Always write LCTL after LAR.
Page 350 9 Link Ports /*_______________Link buffer 2 Rx Interrupt Routine_____________________*/ lp2_orig_slave: /*_______________Allow for pulldown delay on LxACK of the slave_________________*/ bit clr imask LSRQI; /* Disable Link port service request interrupt r0=0x10; dm(LSRQ)=r0; /* Unmask LSRQ lport 0 transmit request status r0=0x00000000;...
Page 351 Link Ports r0=0x00000100; dm(LCTL)=r0; /* LBUF2=rx (slave), No DMA bit clr mode1 NESTM; /* disable interrupt nesting /* to avoid breaking sync r0=dm(LBUF2); /* read token permission from master /* The following check if the first word after DMA is token */ /* permission.
Page 352 9 Link Ports /*_______________Protection to avoid two transmitting link ports________________*/ bit clr imask LSRQI; /* Disable Link port service request interrupt r0=0x10; dm(LSRQ)=r0; /* Unmask LSRQ lport 0 transmit request status r0=0x00000000; dm(LCTL)=r0; /* LCTL: disable all LBUFs disabled3: r0=dm(LSRQ); /* Check to ensure that the pull down on LxACK r0=FEXT r0 BY 20:1;...
Page 353 Link Ports r0=0xc0; wait: r1=dm(LCOM); /* check if LBUF3 is empty r0=r0 AND r1; if NE jump wait; /* if DMA size not thru, wait nop; r0=source_3; dm(II5)=r0; /* Tx DMA setup r0=1; dm(IM5)=r0; /* Set modify to 1 r0=@source_3; dm(C5)=r0;...
Page 354 9 Link Ports r0=destination_2; dm(II5)=r0; /* Set DMA rx index to start of dest buffer r0=1; dm(IM5)=r0; /* Set modify to 1 r0=@destination_2; dm(C5)=r1; /* real DMA Rx size should be got from master r0=0x00003000; /* LCTL Register:32-bit data, LBUF3=Rx dm(LCTL)=r0;...
Page 355 Link Ports bit set imask LP2I; /* Enable Link buffer 2 interrupt bit set mode1 IRPTEN; /* Global interrupt enable r0=0x00000300; /* LCTL Register:32-bit data, LBUF2=Rx dm(LCTL)=r0; /* enable DMA on LBUF2 /* This will start off the DMA transfer /* Always write LCTL after LAR wait_2: idle;...
Page 356 9 Link Ports 9 – 46 www.BDTIC.com/ADI...
Page 357: Overview
Serial Ports 10.1 OVERVIEW The ADSP-2106x has two independent, synchronous serial ports, SPORT0 and SPORT1, that provide an I/O interface to a wide variety of peripheral devices. Each serial port has its own set of control registers and data buffers. With a range of clock and frame synchronization options, the SPORTs allow a variety of serial communication protocols and provide a glueless hardware interface to many industry-standard data converters and CODECs.
Page 358: Table 10.1 Serial Port Pins
10 Serial Ports • DMA transfers to and from on-chip memory—each SPORT can automatically receive and/or transmit an entire block of data. • Chained DMA operations of multiple data blocks. • Multichannel mode for TDM interfaces—each SPORT can receive and transmit data selectively from channels of a time-division-multiplexed serial bitstream;...
Page 359: Figure 10.1 Serial Port Block Diagram
Serial Ports framing signals are used, the TFS signal indicates the start of the serial word transmission. The DT pin is always driven, i.e. not tristated, if the serial port is enabled (SPEN=1 in the STCTLx control register), unless it is in multichannel mode and an inactive time slot occurs. (See Section 10.7, “Multichannel Operation.”) The receive portion of the SPORT shifts in data from the DR pin, synchronous to the RCLK receive clock.
Page 360: Sport Interrupts
10 Serial Ports 10.1.1 SPORT Interrupts Each serial port has a transmit DMA interrupt and a receive DMA interrupt. When serial port DMA is not enabled, the interrupts occur for each data word transmitted and received. The priority of the serial port interrupts is shown in Table 10.2.
Page 361: Sport Control Registers & Data Buffers
Serial Ports 10.3 SPORT CONTROL REGISTERS & DATA BUFFERS The registers used to control and configure the serial ports are part of the IOP register set. Each SPORT has its own set of the following control registers and data buffers: Register Name* Function...
Page 362: Register Writes & Effect Latency
10 Serial Ports Memory Register Initialization Address Name After RESET Description 0x00E0 STCTL0 0x0000 0000 SPORT0 Transmit Control Register 0x00E1 SRCTL0 0x0000 0000 SPORT0 Receive Control Register 0x00E2 SPORT0 Transmit Data Buffer 0x00E3 SPORT0 Receive Data Buffer 0x00E4 TDIV0 SPORT0 Transmit Divisor 0x00E5 reserved 0x00E6...
Page 363: Transmit & Receive Data Buffers (Tx, Rx)
Serial Ports After a write to a SPORT register, control and mode bit changes generally take effect in the second CLKIN cycle after the write is completed. The serial ports will be ready to start transmitting or receiving two CLKIN cycles after they are enabled (in the STCTLx or SRCTLx control register).
Page 364: Reading & Writing Rx, Tx
10 Serial Ports An interrupt is generated when the RX buffer has been loaded with a received word (i.e. the RX buffer is “not empty”). This interrupt will be masked out if serial port DMA is enabled or if the corresponding bit in the IMASK register is set.
Page 365: Table 10.4 Stctlx Transmit Control Register Bits
Serial Ports The TXS status bits indicate whether the TX buffer is full (11), empty (00), or partially full (10). To test for space in TX, therefore, test for TXS0 (bit 30) equal to zero. To test for the presence of any data in TX, test for TXS1 (bit 31) equal to one.
Page 366: Figure 10.2 Stctl0, Stctl1 Transmit Control Registers
10 Serial Ports 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 LTFS Active Low TFS TX Data Buffer Status (read-only) 1=active low, 0=active high 11=full, 00=empty, 10=partially full LAFS* TUVF Late TFS Transmit Underflow Status (sticky, read-only) 1=late TFS, 0=early TFS SDEN CHNL...
Page 367: Table 10.5 Srctlx Receive Control Register Bits
Serial Ports Bit(s) Name Definition SPEN* SPORT Enable DTYPE Data Type (data format, companding) SENDN Serial Word Endian (1=LSB first) SLEN Serial Word Length – 1 PACK Data Word Packing (16-bit to 32-bit) ICLK Internally Generated Receive Clock – reserved CKRE Data, Frame Sync Sampling on Clock Rising Edge RFSR*...
Page 368: Figure 10.3 Srctl0, Srctl1 Receive Control Registers
10 Serial Ports 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 LRFS Active Low RFS RX Data Buffer Status (read-only) 1=active low, 0=active high 11=full, 00=empty, 10=partially full LAFS* ROVF Late RFS Receive Overflow Status (sticky, read-only) 1=late RFS, 0=early RFS SDEN SPORT Receive DMA Enable...
Page 369: Clock & Frame Sync Frequencies (Tdiv, Rdiv)
Serial Ports 10.3.4 Clock & Frame Sync Frequencies (TDIV, RDIV) The TDIVx and RDIVx registers contain divisor values which determine the frequencies for internally generated clocks and frame syncs. These registers are defined in Tables 10.6 and 10.7, and are pictured in Figures 10.4 and 10.5.
Page 370: Figure 10.5 Rdiv0, Rdiv1 Receive Divisor Registers
10 Serial Ports RFSDIV Receive Frame Sync Divisor RCLKDIV Receive Clock Divisor Figure 10.5 RDIV0, RDIV1 Receive Divisor Registers TCLKDIV and RCLKDIV specify how many times the ADSP-2106x system clock (CLKIN) is divided to generate the transmit and receive clocks. The divisor is a 16-bit value, allowing a wide range of serial clock rates.
Page 371: Maximum Clock Rate Restrictions
Serial Ports The formula for the number of cycles between frame synch pulses is: # of serial clock cycles between frame sync assertions = xFSDIV + 1 Use the following equation to determine the value of xFSDIV to use, given the serial clock frequency and desired frame sync frequency: serial clock frequency xFSDIV = ——————————...
Page 372: Data Word Formats
10 Serial Ports 10.4 DATA WORD FORMATS The format of the data words transmitted over the serial ports is configured by the DTYPE, SENDN, SLEN, and PACK bits of the STCTLx and SRCTLx control registers. 10.4.1 Word Length The serial ports handle word lengths of 3 to 32 bits. The word length is configured in the 5-bit SLEN field in the STCTLx and SRCTLx control registers.
Page 373: Data Type
Serial Ports The first 16-bit (or smaller) word is right-justified in bits 15-0 of the packed word, and the second 16-bit (or smaller) word is right-justified in bits 31-16. This applies for both receive (packing) and transmit (unpacking) operations. Companding may be used when word packing or unpacking is being used.
Page 374: Companding
10 Serial Ports Transmit sign extension is selected by bit 0 of DTYPE in the STCTLx register and is common to all transmit channels. Receive sign extension is selected by bit 0 of DTYPE in the SRCTLx register and is common to all receive channels.
Page 375: Clock Signal Options
Serial Ports To expand data in-place, the same sequence of operations is used but with RX rather than TX. When expanding data in this way, be sure that the serial word length (SLEN) is set appropriately in the SRCTLx control register. With companding enabled, interfacing the ADSP-2106x serial port to a codec requires little additional programming effort.
Page 376: Frame Sync Options
10 Serial Ports 10.6 FRAME SYNC OPTIONS Framing signals indicate the beginning of each serial word transfer. The framing signals for each serial port are TFS (transmit frame synchronization) and RFS (receive frame synchronization). A variety of framing options are available; these options are configured in the serial port control registers.
Page 377: Internal Vs. External Frame Syncs
Serial Ports xCLK Framed Data Unframed Data Figure 10.6 Framed vs. Unframed Data 10.6.2 Internal vs. External Frame Syncs Both transmit and receive frame syncs can be independently generated internally or input from an external source. The ITFS and IRFS bits of the STCTLx and SRCTLx control registers determine the frame sync source.
Page 378: Active Low Vs. Active High Frame Syncs
10 Serial Ports 10.6.3 Active Low vs. Active High Frame Syncs Frame sync signals may be either active high or active low (i.e. inverted). The LTFS and LRFS bits of the STCTLx and SRCTLx control registers determine the frame syncs’ logic level. When LTFS=0 or LRFS=0, the corresponding frame sync signal will be active high.
Page 379: Early Vs. Late Frame Syncs
Serial Ports 10.6.5 Early vs. Late Frame Syncs Frame sync signals can occur during the first bit of each data word (“late”) or during the serial clock cycle immediately preceding the first bit (“early”). The LAFS bit of the STCTLx and SRCTLx control registers configures this option.
Page 380: Data-Independent Transmit Frame Sync
10 Serial Ports Figure 10.7 illustrates the two modes of frame signal timing: • LAFS bits of STCTLx, SRCTLx control registers. LAFS=0 for early frame syncs, LAFS=1 for late frame syncs. • Early framing: frame sync precedes data by one cycle. Late framing: frame sync checked on first bit only.
Page 381: Multichannel Operation
Serial Ports When DITFS=1, the internally generated TFS is output at its programmed interval regardless of whether new data is available in the TX buffer. Whatever data is present in TX will be retransmitted with each assertion of TFS. The TUVF transmit underflow status bit (in the STCTLx control register) will be set when this occurs (i.e.
Page 382: Frame Syncs In Multichannel Mode
10 Serial Ports Figure 10.8 shows example timing for a multichannel transfer, which have the following characteristics: • Uses TDM method where serial data is sent or received on different channels sharing the same serial bus. • The number of channels is selected with the NCH bits of SRCTLx: NCH=(# of channels) –...
Page 383: Multichannel Control Bits In Stctl, Srctl
Serial Ports whether or not DTx is being driven by the ADSP-2106x. The ADSP- 2106x drives TFS in multichannel mode whether or not ITFS is cleared. After the TX transmit buffer is loaded, transmission begins and the TFS signal is generated. When serial port DMA is being used, this may happen several cycles after the multichannel transmission is enabled.
Page 384: Multichannel Frame Delay
10 Serial Ports 10.7.2.4 Multichannel Frame Delay The 4-bit MFD field in the STCTLx control register specifies a delay between the frame sync pulse and the first data bit in multichannel mode. The value of MFD is the number of serial clock cycles of the delay. Multichannel frame delay allows the processor to work with different types of T1 interface devices.
Page 385: Sport Receive Comparison Registers
Serial Ports Setting a particular bit to 1 in the MTCSx register causes the serial port to transmit the word in that channel’s position of the data stream. Clearing the bit to 0 in the MTCSx register causes the serial port’s DT (data transmit) pin to tristate during the time slot of that channel.
Page 386: Serial Ports
10 Serial Ports When receive comparison is enabled, companding is disabled on the transmitter and receiver. The MTCCSx register, which selects multichannel companding when receive comparison is disabled, determines whether the DSP performs a KEYWD comparison for the enabled received channels. If the MTCCSx bit for a particlular channel is '0,' the processor does not perform a comparison and always accepts the receive data on that channel.
Page 387: Transferring Data Between Sports And Memory
Serial Ports Processor B can check for this key word as follows: Set the KEYWD register to "START TRANSMIT TO B" Clear bits 31:16 of the KEYMASK register to 0 and set the other bits to 1 This step enables comparison only for bits 31:16. So, assume that the code for "START TRANSMIT TO B"...
Page 388: Dma Block Transfers
10 Serial Ports When serial port DMA is not enabled in the STCTLx or SRCTLx control registers, the SPORT generates an interrupt every time it has received a data word or has started to transmit a data word. SPORT DMA provides a mechanism for receiving or transmitting an entire block of serial data before the interrupt is generated.
Page 389: Sport Dma Channel Setup
Serial Ports 10.8.1.1 SPORT DMA Channel Setup Each SPORT DMA channel has an enable bit (SDEN) in the STCTLx and SRCTLx control registers of the two serial ports. When DMA is not enabled for a particular channel, the SPORT generates an interrupt every time it has received a data word or has started to transmit a data word (see “Single-Word Transfers”...
Page 390: Table 10.8 Parameter Registers For Each Sport Dma Channel
10 Serial Ports Each DMA channel has a count register (C) which must be initialized with a word count to be transferred. The count register is decremented after each DMA transfer on that channel; when the count reaches zero, the interrupt for that channel is generated and the channel is automatically disabled.
Page 391: Sport Dma Chaining
Serial Ports Memory Address Register Channel Number & Function 0x0060 DMA Channel 0 – SPORT0 Receive 0x0061 DMA Channel 0 – SPORT0 Receive 0x0062 DMA Channel 0 – SPORT0 Receive 0x0063 DMA Channel 0 – SPORT0 Receive 0x0064 DMA Channel 0 – SPORT0 Receive 0x0065 DMA Channel 0 –...
Page 392: Single-Word Transfers
10 Serial Ports DMA chaining occurs independently for the transmit and receive channels of each serial port. Each SPORT DMA channel has a chaining enable bit (SCHEN) in the STCTLx and SRCTLx control registers. This bit must be set to 1 to enable chaining. Writing all zeros to the address field of the chain pointer register (CP) also disables chaining.
Page 393: Sport Pin Driver Concerns
Serial Ports When loopback is configured, the DRx, RCLKx, and RFSx signals of the receive section of the SPORT are internally connected to the DTx, TCLKx, and TFSx signals of the transmit section. The DTx, TCLKx, and TFSx signals are active and are available at their respective pins, while the DRx, RCLKx, and RFSx pins are ignored by the ADSP-2106x.
Page 394: Listing 10.1 Non-Interrupt-Driven Sport Control (Single-Word Transfers)
10 Serial Ports /*_________________________________________________________________ SPORT Transmit Example: Uses the feature that the ADSP-2106x core will stall when attempting to write to a full TX register. This example sets up a loop to transmit the data in the memory buffer “source”. ________________________________________________________________*/ #define N 8 #include “def21060.h”...
Page 395: Single-Word Transfers With Interrupts
Serial Ports 10.11.2 Single-Word Transfers With Interrupts While the non-interrupt-driven solution of the previous example provides a very simple control scheme, it prevents the ADSP-2106x processor core from handling any additional tasks while it is stalled. In most real-time applications, the DSP must process data while new data is being received.
Page 396: Listing 10.2 Interrupt-Driven Sport Control (Single-Word Transfers)
10 Serial Ports /*_________________________Main routine_________________________*/ .segment/pm pm48_1b0; /* Main code segment from arch file.*/ start: r0=0x00270007; /* TDIV0 Register: TCLKDIV=7,TFSDIV=39 */ dm(TDIV0)=r0; /* sclock=CLKIN/8, framerate=sclock/20 */ r0=0x000064f1; /* STCTL0 Register: dm(STCTL0)=r0; /* SPEN=1,(SPORT enabled)*/ /* SLEN=15 (16-bit word)*/ /* ICLK=1, (internal tx clock)*/ /* TFSR=1, (require TFS)*/ /* ITFS=1, (internal TFS)*/ /* DITFS=0,(data dependent FS)*/...
Page 397: Dma Transfers With Interrupts
Serial Ports 10.11.3 DMA Transfers With Interrupts This example shows how to use the ADSP-2106x’s on-chip DMA controller to handle serial port I/O. The DMA controller performs the data transfers between internal memory and the SPORTs, providing the most efficient way to handle input and output of multiple-word blocks of data.
Page 398: Listing 10.3 Sport Dma Example
10 Serial Ports /*________________________main routine________________________*/ .segment/pm pm48_1b0; /* Main code segment from arch. file*/ start: r0=source; dm(II3)=r0; /* Set DMA tx index to start of source buffer*/ r0=destination; dm(II1)=r0; /* Set DMA rx index to start of destination buffer*/ r0=1; dm(IM3)=r0;...
Page 399: Overview
System Design 11.1 OVERVIEW This chapter provides hardware, software, and system design information. 11.2 ADSP-2106X PINS This section describes the pins of the ADSP-2106x and shows how these signals can be used in your system. Figure 11.1 illustrates how the pins are used in a single-processor system. Figure 7.1 in the Multiprocessing chapter shows a system diagram illustrating pin connections in an ADSP-2106x multiprocessor cluster.
Page 400: Pin Definitions
11 System Design 11.2.1 Pin Definitions ADSP-2106x pin definitions are listed below. All pins are identical on the ADSP-21060 and ADSP-21062. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be TRST asserted asynchronously to CLKIN (or to TCK for Unused inputs should be tied or pulled to VDD or GND, except for...
Page 401 System Design Type Function I/O/T Memory Read Strobe. This pin is asserted (low) when the ADSP-2106x reads from external memory devices or from the internal memory of other ADSP-2106xs. External devices (including other ADSP-2106xs) must assert read from the ADSP-2106x’s internal memory. In a multiprocessing system, is output by the bus master and is input by all other ADSP-2106xs.
Page 402 11 System Design Type Function I/O/S Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access.
Page 403 System Design Type Function Chip Select. Asserted by host processor to select the ADSP-2106x. REDY (o/d) O Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain output (o/d) by default;...
Page 404 11 System Design Type Function (o/d) Core Priority Access. Asserting its pin allows the core processor of an ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus. is an open drain output that is connected to all ADSP-2106xs in the system.
Page 405 System Design Type Function I/O/T* Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT=1, LBOOT=0). In a multiprocessor system, is output by the bus master. Input: When low, indicates that no booting will occur and that ADSP- 2106x will begin executing instructions from external memory.
Page 406 11 System Design Type Function Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only. ICSA Reserved, leave unconnected. Power Supply; nominally +5.0V dc for 5V devices or +3.3V dc for 3.3V devcies. (30 pins) Power Supply Return. (30 pins) Do Not Connect.
Page 407: Pin States At Reset
System Design Figure 11.a shows how different data word sizes are transferred over the external port. DATA 47-0 EPROM Boot 16-Bit Packed 32-Bit Float or Fixed, D31 - D0, 32-Bit Packed 40-Bit Extended Float Instruction Fetch Figure 11.a External Port Data Alignment 11.2.2 Pin States At Reset Table 11.1 shows the ADSP-2106x pin states during and immediately after reset.
Page 408: Reset & Clkin
11 System Design Type State During & After RESET Bus-Master-Independent: REDY (o/d) Tristate DMAR1 Input DMAR2 Input Inputs RPBA Input (o/d) Tristate EBOOT Input LBOOT Input (must be tied to GND on the ADSP-21061) I/O/T Input CLKIN Input RESET Input Serial Ports &...
Page 409: Input Synchronization Delay
System Design 11.2.3.1 Input Synchronization Delay RESET TRST The ADSP-2106x has several asynchronous inputs: DMAR1 DMAR2 , and FLAG (when configured as inputs). These inputs can be asserted in arbitrary phase to the processor clock, CLKIN. The ADSP-2106x synchronizes the inputs prior to recognizing them.
Page 410: Flag Inputs
11 System Design The flags are bidirectional pins, each with the same functionality. To program the direction of each flag pin, the following control bits in the MODE2 register are used: MODE2 Name Definition FLG0O FLAG0 direction (1=output, 0=input) FLG1O FLAG1 direction (1=output, 0=input) FLG2O FLAG2 direction (1=output, 0=input)
Page 411: Flag Outputs
System Design 11.2.5.2 Flag Outputs When a flag is configured as an output, the value on the pin follows the value of the corresponding bit in the ASTAT register. Your program can set or clear the ASTAT flag bit to provide a signal to another processor or peripheral.
Page 412: Ez-Ice Emulator
11 System Design 11.3 EZ-ICE EMULATOR The ADSP-2106x EZ-ICE Emulator is a development tool for debugging programs running in real time on your ADSP-2106x target system hardware. The EZ-ICE provides a controlled environment for observing, debugging, and testing activities in a target system by connecting directly to the target processor through its JTAG interface.
Page 413 System Design × Key (no pin) CLKIN (optional) BTMS BTCK TRST BTRST BTDI Top View Figure 11.3 Target Board Connector For ADSP-2106x EZ-ICE Emulator (Jumpers In Place) BTRST The BTMS, BTCK, , and BTDI signals are provided so that the test access port can also be used for board-level testing.
Page 414: Figure 11.4 Jtag Scan Path Connections For Multiprocessor Adsp-2106X Systems
11 System Design Figure 11.4 shows JTAG scan path connections for systems that contain multiple ADSP-2106x processors. Connecting CLKIN to pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when performing synchronous multiprocessor operations such as starting, stopping, and single-stepping multiple ADSP-2106xs. If you do not need these operations to occur synchronously on the multiple processors, simply tie pin 4 of the EZ-ICE header to ground.
Page 415: Input Signal Conditioning
System Design 11.4 INPUT SIGNAL CONDITIONING The ADSP-2106x SHARC processor is a CMOS device. It has input conditioning circuits which simplify system design by filtering or latching input signals to reduce susceptibility to glitches or reflections. The following sections describe why these circuits are needed and their effect on input signals.
Page 416: High Frequency Design Considerations
The small amount of hysteresis allowable is due to the restrictions on the tolerance of the V and V TTL input levels under worst case conditions. Refer to the ADSP-2106x SHARC Data Sheet for exact specifications. 11.5 HIGH FREQUENCY DESIGN CONSIDERATIONS...
Page 417: Clock Specifications & Jitter
System Design 11.5.1 Clock Specifications & Jitter The clock signal must be free of ringing and jitter. Clock jitter can easily be introduced in a system where more than one clock frequency exists. High frequency jitter on the clock to the ADSP-2106x may result in abbreviated internal cycles.
Page 418 11 System Design +5 V 180 Ω 50 Ω Transmission Line 1.4 V Clock 70 Ω ADSP-2106x ADSP-2106x ADSP-2106x Figure 11.5 Not Recommended Clock Distribution Method (End-Of-Line Termination) For source termination (2), Figure 11.6 shows an example of series-terminated transmission lines for clock distribution. This allows delays in each path to be identical.
Page 419: Point-To-Point Connections
System Design ACTQ240 Octal Inverter (National Semiconductor) IDT49FCT805/A CY7C992 40 Ω 50 Ω Transmission Line ADSP-2106x 40 Ω 50 Ω Transmission Line Clock ADSP-2106x 40 Ω 50 Ω Transmission Line ADSP-2106x Buffer Drive Impedance = 10 Ω A separate buffer and transmission line is needed for each group of processors that are further than 4 inches from each other.
Page 420: Signal Integrity
11 System Design ADSP-2106x ADSP-2106x 33 Ω 33 Ω 50 Ω Transmission Line (Length > 6") Driver Impedance = 17 Ω Open Circuit Link Port Link Port Transmitter Receiver Reflected wave is absorbed at the source. Figure 11.7 Source Termination For Long-Distance Point-To-Point Connections 11.5.4 Signal Integrity The capacitive loading on high-speed signals should be reduced as...
Page 421: Figure 11.8 Star Connection Damping Resistors
System Design ADSP-2106x ADSP-2106x 10 Ω each ADSP-2106x ADSP-2106x Figure 11.8 Star Connection Damping Resistors ADSP-2106x ADSP-2106x 20 Ω ADSP-2106x ADSP-2106x Figure 11.9 Single Damping Resistor Between Processor Groups 11 – 23 www.BDTIC.com/ADI...
Page 422: Other Recommendations & Suggestions
11 System Design an impedance of 25Ω, but this resistor is biased at 1.4V so the drive from the ADSP-2106xs will be sufficient for TTL levels. To reduce power dissipation in the system and in each ADSP-2106x, this should only be used, if necessary, for signals such as the strobe.
Page 423: Decoupling Capacitors & Ground Planes
System Design • The use of 3.3V components and power supplies will help transmission line problems significantly because the receiver switching voltage of 1.5V is close to the middle of the voltage swing. In addition, ground bounce and noise coupling will be less. The ADSP-2106x is available in a 3.3V version.
Page 424: Oscilloscope Probes
11 System Design type or similarly short (< 0.5 inch) ground clip, attached to the tip of the oscilloscope probe. The probe should be a low-capacitance active probe with 3 pF or less of loading. The use of a standard ground clip with 4 inches of ground lead will cause ringing to be seen on the displayed trace and will make the signal appear to have excessive overshoot and undershoot.
Page 425: Booting
Because most applications require more than 256 words of instructions and initialization data, the 256 words typically serve as a loading routine for the application. Analog Devices supplies a loading routine (Loader Kernel) that can load an entire program.
Page 426: Table 11.2 Boot Mode Selection Pins
11 System Design Type Description EBOOT EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-bit EPROM. When EBOOT is low, the LBOOT and inputs determine booting mode. See table below. This signal is a system configuration selection which should be hardwired.
Page 427: Eprom Booting
System Design host boot mode or no boot mode. In EPROM boot mode, deasserted when the ADSP-2106x is not the bus master. Note that when using any of the power-up booting modes, address 0x0002 0004 should not contain a valid instruction since it is not executed during the booting sequence.
Page 428: For Eprom Booting
11 System Design SHARC could latch acknoledge low. The SHARC responds to the deasserted (low) acknowledge as a hold off from the EPROM, inserting wait states continually and preventing completion of the EPROM boot. To avoid this type of boot holdoff, change the value in the WAIT register, setting the UBWM value to internal wait mode (01) early in the 256 word boot process.
Page 429: Loading The Remaining Eprom Data
System Design selected by the pin; other memory select pins are disabled. The DMA external count register (EC6) decrements after each EPROM transfer. When EC6 reaches zero, the following wake-up sequence occurs: 1. The DMA transfers stop. 2. The External Port DMA Channel 6 interrupt (EP0I) is activated. is deactivated and normal external memory selects are activated.
Page 430: Writing To Bms Memory Space
11 System Design when BSO is set.) While one of the external port DMA channels is being used in conjunction with the BSO bit, none of the other three channels may be used. When BSO=1, is not asserted by a core processor access, only by a DMA transfer.
Page 431: Table 11.4 Ext. Port Dma Channel 6 Parameter Register Initialization For Host Booting
System Design words, PMODE for 16-to-48 bit word packing, and least-significant- word first. Because the host processor is accessing the EPB0 external port buffer, the HPM host packing mode bits of the SYSCON register must be set to correspond to the external bus width specified by the PMODE bits of the DMAC6 control register.
Page 432: Link Port Booting
11 System Design return execution to the reset routine at location 0x0002 0005 where normal program execution can resume. After this 256 word load and RTI have occurred, your program can write a different service routine at the EP0I vector location 0x0002 0040. These 256 instructions must serve as a loader that loads the rest of your program.
Page 433: Multiprocessor Booting
System Design 11.6.5 Multiprocessor Booting Multiprocessor systems can be booted from a host processor, from external EPROM, through a link port, or from external memory. 11.6.5.1 Multiprocessor Host Booting To boot multiple ADSP-2106x processors from a host, each ADSP-2106x must have its EBOOT, LBOOT, and pins configured for host booting: EBOOT=0, LBOOT=0, and =1.
Page 434: Processors-Take-Turns
11 System Design ADDR ADDR 31-0 EBOOT DATA 23-16 LBOOT DATA DATA 47-0 ADSP-2106x (S1, Master) EPROM ADDR 31-0 EBOOT DATA 47-0 LBOOT ADSP-2106x (S2, Slave) ADDR 31-0 EBOOT DATA 47-0 LBOOT ADSP-2106x (S6, Slave) Figure 11.12 Multiple SHARCs Booting From One EPROM, Processors-Take-Turns ADDR ADDR 31-0...
Page 435: Multiprocessor Link Port Booting
System Design One ADSP-2106x is booted, which then boots the others. The EBOOT pin of the ADSP-2106x with ID=1 must be set high for EPROM booting. All other ADSP-2106xs should be configured for host booting (EBOOT=0, LBOOT=0, and =1), which leaves them in the idle state at startup and allows the ADSP-2106x with ID=1 to become bus master and boot itself.
Page 436: Important Programming Reminders
11 System Design The IIVT bit in the SYSCON control register can be used to override the booting mode in determining where the interrupt vector table is located. If the ADSP-2106x is not booted (no boot mode), setting IIVT to 1 selects an internal vector table while IIVT=0 selects an external vector table.
Page 437: Program Memory Data Access In Loops
System Design 11.7.1.3 Program Memory Data Access In Loops The ADSP-2106x caches an instruction that it needs to fetch during the execution of a PM bus data access. Because of the execution pipeline, this instruction is usually two memory locations after the PM bus data access.
Page 438: One- & Two-Instruction Loops
11 System Design 11.7.1.4 One- & Two-Instruction Loops Counter-based loops that have only one or two instructions can cause delays if not executed a minimum number of times. The ADSP-2106x checks the termination condition two cycles before it exits the loop. In these short loops, the ADSP-2106x has already looped back when the termination condition is tested.
Page 439: Circular Buffer Initialization
System Design delayed branch instruction and either of the two instructions that follow is not processed until the branch is complete. Delayed branching can be used with the JUMP, CALL, RTS, and RTI instructions. For delayed JUMPs, the following instructions may not be used in the two locations immediately after the jump: •...
Page 440: Two Writes To Register File
11 System Design 11.7.5 Two Writes To Register File If two writes to the same register file location take place in the same cycle, only the write with higher precedence actually occurs. Precedence is determined by the source of the data being written; from highest to lowest, the precedence is: •...
Page 441: Mixing 32-Bit & 48-Bit Words In A Memory Block
System Design 11.7.8 Mixing 32-Bit & 48-Bit Words In A Memory Block 32-bit data words and 48-bit instruction words can be stored in the same memory block, with the restriction that all instructions must reside at addresses lower than the data. No instruction may be stored at an address higher than the lowest address of any data word.
Page 442: Data Delays, Latencies, & Throughput
11 System Design To assure single-cycle, parallel accesses of two on-chip memory locations, the following conditions must be met: • The two addresses must be located in different memory blocks (i.e. one in Block 0, one in Block 1). • One address must be generated by DAG1 and the other by DAG2. •...
Page 443 System Design Memory Stalls • 1 cycle on PM and DM bus accesses to the same block of internal memory • n cycles if conflicting accesses to external memory (PM and DM bus accesses must complete) • n cycles if access to external memory (until I/O buffers are cleared out) •...
Page 444: Table 11.5 Data Delays & Throughputs
11 System Design Minimum Maximum Data Delay Throughput Operation (cycles) (cycles/transfer) Core Processor Access to External Memory Synchronous Access of Slave’s IOP Registers* –Read (Transfer Out) –Write (Transfer In) Delay is between data in the IOP register and at the External Port (e.g.
Page 445: Table 11.6 Latencies & Throughputs
System Design Minimum Maximum Latency Throughput Operation (cycles) (cycles/transfer) Interrupts ( – Multiprocessor Bus Requests ( – Host Bus Request ( – SYSCON Effect Latency – Host Packing Status Update (in SYSTAT register) – DMA Packing Status Update (in DMACx register) –...
Page 446 11 System Design 11 – 48 www.BDTIC.com/ADI...
Page 447: A.1 Overview
Instruction Set Reference OVERVIEW This appendix and the next one describe the ADSP-2106x instruction set in detail. This appendix explains each instruction type, including the assembly language syntax and the opcode that the instruction assembles to. Many instruction types contain a field for specifying a compute operation (an operation that uses the ALU, multiplier or shifter).
Page 448: A.2 Instruction Set Summary
Instruction Set Reference INSTRUCTION SET SUMMARY The next few pages summarize the ADSP-2106x instruction set. The compute operations used within each instruction are specified in Appendix B. Compute & Move or Modify Instructions compute, DM(Ia,Mb) = dreg1 , PM(Ic,Md) = dreg2 ; (pg.
Page 449 Instruction Set Reference Program Flow Control Instructions (pg. A-28) IF condition JUMP <addr24> (DB) (PC, <reladdr24>) (LA) (CI) (DB,LA) (DB,CI) IF condition CALL <addr24> (DB) ; (PC, <reladdr24>) (pg. A-30) IF condition JUMP (Md,Ic) (DB) compute (PC, <reladdr6>) (LA) ELSE compute (CI) (DB,LA) (DB,CI)
Page 450 Instruction Set Reference Immediate Move Instructions 14a. DM(<addr32>) = ureg ; (pg. A-40) PM(<addr24>) 14b. ureg = DM(<addr32>) PM(<addr24>) 15a. DM(<data32>, Ia) = ureg ; (pg. A-41) PM(<data24>, Ic) 15b. ureg = DM(<data32>, Ia) ; PM(<data24>, Ic) DM(Ia,Mb) = <data32> ; (pg.
Page 451 Instruction Set Reference Instruction Set Notation Notation Meaning UPPERCASE Explicit syntax—assembler keyword (notation only; assembler is case-insensitive and lowercase is the preferred programming convention) Semicolon (instruction terminator) Comma (separates parallel operations in an instruction) italics Optional part of instruction option1 List of options between vertical bars (choose one) option2 compute...
Page 452 Instruction Set Reference Universal Registers Register Function Data Register File R15 - R0 Register file locations, fixed-point F15 - F0 Register file locations, floating-point Program Sequencer Program counter (read-only) PCSTK Top of PC stack PCSTKP PC stack pointer FADDR Fetch address (read-only) DADDR Decode address (read-only) LADDR...
Page 453 Instruction Set Reference Memory Addressing in Instructions Direct: Absolute Instruction Types 8, 12, 13, 14 Examples: dm(0x000015F0) = astat; if ne jump label2; {'label2' is an address label} PC-relative Instruction Types 8, 9, 10, 12, 13 Examples: call(pc,10), r0=r6+r3; do(pc,length) until sz; {'length' is a variable} Register Indirect (using DAG registers): Post-modify with M register, update I register...
Page 454: A.3 Opcode Notation
Instruction Set Reference OPCODE NOTATION In ADSP-2106x opcodes, some bits are explicitly defined to be zeros or ones. The values of other bits or fields set various parameters for the instruction. The terms in this section define these opcode bits and fields. Bits which are unspecified are ignored when the processor decodes the instruction, but are reserved for future use.
Page 455 Instruction Set Reference Computation unit select codes Multiplier Shifter DATA Immediate data field Counter decrement code No counter decrement Counter decrement Memory access direction Read Write Index (I) register numbers, DAG1 0 - 7 Modify (M) register numbers, DAG1 0 - 7 DREG Register file locations 0 - 15...
Page 456 Instruction Set Reference Jump Type Non-delayed Delayed Loop stack pop code No stack pop Stack pop Loop stack push code No stack push Stack push Loop reentry code No loop reentry Loop reentry Interrupt vector 0 - 7 OPCODE Computation unit opcodes (see Appendix B) Memory access direction Read Write...
Page 457 Instruction Set Reference RELADDR PC-relative address field Status stack pop code No stack pop Stack pop Status stack push code No stack push Stack push System Register code SREG 0 - 15 (see “Universal Register Codes” on the next page) TERM Termination Condition codes 0 - 31...
Page 458: A.4 Universal Register Codes
Instruction Set Reference UNIVERSAL REGISTER CODES Map 1 Registers: program counter System Registers: PCSTK top of PC stack MODE1 mode control 1 PCSTKP PC stack pointer MODE2 mode control 2 FADDR fetch address IRPTL interrupt latch DADDR decode address IMASK interrupt mask LADDR loop termination address...
Page 459 Instruction Set Reference Map 2 Registers: 48-bit PX1 and PX2 combination bus exchange 1 (16 bits) bus exchange 2 (32 bits) TPERIOD timer period TCOUNT timer counter (b7=1) b7 b6 b5 b4 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0...
Page 460 Instruction Set Reference A – 14 www.BDTIC.com/ADI...
Page 461: Group I. Compute And Move Instructions
Instruction Set Reference Group I. Compute and Move Instructions 1. Parallel data memory and program memory transfers with register file, optional compute operation ....................A-16 2. Compute operation, optional condition ..............A-17 3. Transfer between data or program memory and universal register, optional condition, optional compute operation ..............A-18 4.
Page 462: Compute / Dreg÷Dm / Dreg÷Pm
Compute and Move Instruction Set Reference compute / dreg DM / dreg PM Syntax: compute, DM(Ia, Mb) = dreg1 , PM(Ic, Md) = dreg2 dreg1 = DM(Ia, Mb) dreg2 = PM(Ic, Md) Function: Parallel accesses to data memory and program memory from the register file.
Page 463: Compute
Compute and Move Instruction Set Reference compute Syntax: IF condition compute ; Function: Conditional compute instruction. The instruction is executed if the specified condition tests true. Examples: IF MS MRF=0; F6=(F2+F3)/2; Opcode: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 0 0 0 0 0 0 0 1 COND...
Page 464: Compute / Ureg÷Dm|Pm , Register Modify
Compute and Move Instruction Set Reference compute / ureg DM|PM , register modify Syntax: IF condition compute, DM(Ia, Mb) = ureg ; PM(Ic, Md) IF condition compute, DM(Mb, Ia) = ureg ; PM(Md, Ic) IF condition compute, ureg = DM(Ia, Mb) ; PM(Ic, Md) IF condition compute,...
Page 465 Compute and Move Instruction Set Reference compute / ureg DM|PM , register modify Opcode: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 0 1 0 COND UREG 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
Page 466: Compute / Dreg÷Dm|Pm , Immediate Modify
Compute and Move Instruction Set Reference compute / dreg DM|PM , immediate modify Syntax: IF condition compute, DM(Ia, <data6>) = dreg ; PM(Ic, <data6>) IF condition compute, DM(<data6>, Ia) = dreg ; PM(<data6>, Ic) IF condition compute, dreg = DM(Ia, <data6>) ; PM(Ic, <data6>) IF condition compute,...
Page 467 Compute and Move Instruction Set Reference compute / dreg DM|PM , immediate modify Opcode: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 0 1 1 G D U COND DATA...
Page 468: Compute / Ureg÷Ureg
Compute and Move Instruction Set Reference compute / ureg ureg Syntax: IF condition compute, ureg1 = ureg2 ; Function: Transfer from one universal register to another. If a compute operation is specified, it is performed in parallel with the data access. If a condition is specified, it affects entire instruction.
Page 469 Compute and Move Instruction Set Reference compute / ureg ureg Opcode: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Source Dest 0 1 1 UREG COND UREG...
Page 470: Immediate Shift / Dreg÷Dm|Pm
Compute and Move Instruction Set Reference immediate shift / dreg DM|PM Syntax: IF condition shiftimm DM(Ia, Mb) = dreg ; PM(Ic, Md) IF condition shiftimm dreg = DM(Ia, Mb) PM(Ic, Md) Function: An immediate shift operation is a shifter operation that takes immediate data as its Y-operand.
Page 471 Compute and Move Instruction Set Reference immediate shift / dreg DM|PM Opcode: (with data access) 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 0 0 COND DATAEX...
Page 472: Compute / Modify
Compute and Move Instruction Set Reference compute / modify Syntax: IF condition compute, MODIFY (Ia, Mb) ; (Ic, Md) Function: Update of the specified I register by the specified M register. If a compute operation is specified, it is performed in parallel with the data access. If a condition is specified, it affects entire instruction.
Page 473: Group Ii. Program Flow Control
Instruction Set Reference Group II. Program Flow Control 8. Direct (or PC-relative) jump/call, optional condition ............A-28 9. Indirect (or PC-relative) jump/call, optional condition, optional compute operation ..A-30 10. Indirect (or PC-relative) jump or optional compute operation with transfer between data memory and register file..................A-32 11.
Page 474: Direct Jump|Call
Program Flow Control Instruction Set Reference direct jump|call Syntax: IF condition JUMP <addr24> (PC, <reladdr24>) DB, LA DB, CI IF condition CALL <addr24> (PC, <reladdr24>) Function: A jump or call to the specified address or PC-relative address. The PC- relative address is a 24-bit, twos-complement value. If the delayed branch (DB) modifier is specified, the branch is delayed;...
Page 475 Program Flow Control Instruction Set Reference direct jump|call Examples: IF AV JUMP(PC,0x00A4)(LA); CALL init (DB); {init is a program label} JUMP (PC,2) (DB,CI); {clear current int. for reuse} Opcode: (with direct branch) 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 0 0 0 0 0 1 1 0 COND...
Page 476: Indirect Jump|Call / Compute
Program Flow Control Instruction Set Reference indirect jump|call / compute Syntax: IF condition JUMP (Md, Ic) compute (PC, <reladdr6>) ELSE compute DB, LA DB, CI IF condition CALL (Md, Ic) compute (PC, <reladdr6>) ELSE compute Function: A jump or call to the specified PC-relative address or pre-modified I register value.
Page 477 Program Flow Control Instruction Set Reference indirect jump|call / compute Note: For indirect branches, see Section 4.4.1, “DAG Register Transfer Restrictions”, in Chapter 4, Data Addressing. Examples: JUMP(M8,I12), R6=R6-1; IF EQ CALL(PC,17)(DB) , ELSE R6=R6-1; Opcode: (with indirect branch) 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 0 0 0 0 1 0 0 0 COND...
Page 478: Indirect Jump Or Compute / Dreg÷Dm
Program Flow Control Instruction Set Reference indirect jump or compute / dreg DM Syntax: IF condition JUMP (Md, Ic) , ELSE compute , DM(Ia, Mb) = dreg ; (PC, <reladdr6>) compute , dreg = DM(Ia, Mb) Function: Conditional jump to the specified PC-relative address or pre-modified I register value, or optional compute operation in parallel with a transfer between data memory and the register file.
Page 479 Program Flow Control Instruction Set Reference indirect jump / compute / dreg DM Opcode: (with indirect jump) 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 1 0 COND DREG...
Page 480: Return From Subroutine|Interrupt / Compute
Program Flow Control Instruction Set Reference return from subroutine|interrupt / compute Syntax: IF condition ( DB compute IF condition ( DB compute ELSE compute ELSE compute DB, LR DB, LR IF condition ( DB compute IF condition ( DB compute ELSE compute ELSE compute Function:...
Page 481 Program Flow Control Instruction Set Reference return from subroutine|interrupt / compute Examples: RTI, R6=R5 XOR R1; IF NOT GT RTS(DB); IF SZ RTS, ELSE R0=LSHIFT R1 BY R15; Opcode: (return from subroutine) 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 0 0 0 0 1 0 1 0 COND...
Page 482: Do Until Counter Expired
Program Flow Control Instruction Set Reference do until counter expired Syntax: LCNTR = <data16> , DO <addr24> UNTIL LCE ; ureg (<PC, reladdr24>) Function: Sets up a counter-based program loop. The loop counter LCNTR is loaded with 16-bit immediate data or from a universal register. The loop start address is pushed on the PC stack.
Page 483 Program Flow Control Instruction Set Reference do until counter expired Opcode: (with loop counter load from a universal register) 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 0 0 0 0 1 1 0 1 UREG...
Page 484: Do Until
Program Flow Control Instruction Set Reference do until Syntax: <addr24> UNTIL termination ; (PC, <reladdr24>) Function: Sets up a condition-based program loop. The loop start address is pushed on the PC stack. The loop end address and the termination condition are pushed on the loop stack.
Page 485: Group Iii. Immediate Move
Instruction Set Reference Group III. Immediate Move 14. Transfer between data or program memory and universal register, direct addressing, immediate address................A-40 15. Transfer between data or program memory and universal register, indirect addressing, immediate modifier................A-41 16. Immediate data write to data or program memory ............A-42 17.
Page 486: Ureg÷Dm|Pm (Direct Addressing)
Immediate Move Instruction Set Reference ureg DM|PM (direct addressing) Syntax: DM(<addr32>) = ureg ; PM(<addr24>) ureg = DM(<addr32>) PM(<addr24>) Function: Access between data memory or program memory and a universal register, with direct addressing. The entire data memory or program memory address is specified in the instruction.
Page 487: Ureg÷Dm|Pm (Indirect Addressing)
Immediate Move Instruction Set Reference ureg DM|PM (indirect addressing) Syntax: DM(<data32>, Ia) = ureg ; PM(<data24>, Ic) ureg = DM(<data32>, Ia) ; PM(<data24>, Ic) Function: Access between data memory or program memory and a universal register, with indirect addressing using I registers. The I register is pre-modified with an immediate value specified in the instruction.
Page 488: Immediate Data ' Dm|Pm
Immediate Move Instruction Set Reference immediate data DM|PM Syntax: DM(Ia, Mb) = <data32> ; PM(Ic, Md) Function: A write of 32-bit immediate data to data or program memory, with indirect addressing. The data is placed in the most significant 32 bits of the 40-bit memory word.
Page 489 Immediate Move Instruction Set Reference immediate data ureg Syntax: ureg = <data32> ; Function: A write of 32-bit immediate data to a universal register. If the register is 40 bits wide, the data is placed in the most significant 32 bits, and the least significant 8 bits are loaded with 0s.
Page 490 Instruction Set Reference A – 44 www.BDTIC.com/ADI...
Page 491: Group Iv. Miscellaneous
Instruction Set Reference Group IV. Miscellaneous 18. System register bit manipulation ................A-46 19. Immediate I register modify, with or without bit-reverse ...........A-48 20. Push or Pop of loop and/or status stacks ..............A-50 21. No Operation (NOP) ....................A-51 22. Idle ..........................A-52 23.
Page 492: System Register Bit Manipulation
Miscellaneous Instruction Set Reference system register bit manipulation Syntax: sreg <data32> ; Function: A bit manipulation operation on a system register. This instruction can set, clear, toggle or test specified bits, or compare (XOR) the system register with a specified data value. In the first four operations, the immediate data value is a mask.
Page 493 Miscellaneous Instruction Set Reference system register bit manipulation BIT TST ASTAT 0x00002000; Opcode: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 0 0 0 1 0 1 0 0 SREG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA BOP selects one of the five bit operations.
Page 494: I Register Modify / Bit-Reverse
Miscellaneous Instruction Set Reference I register modify / bit-reverse Syntax: MODIFY (Ia, <data32>) ; (Ic, <data24>) BITREV (Ia, <data32>) ; (Ic, <data24>) Function: Modifies and updates the specified I register by an immediate 32-bit (DAG1) or 24-bit (DAG2) data value. If the address is to be bit-reversed, you must specify a DAG1 register (I0-I7) or DAG2 register (I8-I15), and the modified value is bit-reversed before being written back to the I register.
Page 495 Miscellaneous Instruction Set Reference I register modify / bit-reverse Opcode: (with bit-reverse) 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 0 0 0 1 0 1 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA G selects the data address generator: G=0 for DAG1...
Page 496: Push|Pop Stacks /Flush Cache
Miscellaneous Instruction Set Reference push|pop stacks / flush cache Syntax: PUSH LOOP , PUSH STS , PUSH PCSTK , FLUSH CACHE ; Function: Pushes or pops the loop address and loop counter stacks, the status stack, and/or the PC stack, and/or clear the instruction cache. Any of these options may be combined in a single instruction.
Page 497 Miscellaneous Instruction Set Reference Syntax: NOP; Function: A null operation; only increments the fetch address. Opcode: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A –...
Page 498: Idle
Miscellaneous Instruction Set Reference idle Syntax: IDLE ; Function: Executes a NOP and puts the processor in a low power state. The processor remains in the low power state until an interrupt occurs. On return from the interrupt, execution continues at the instruction following the IDLE instruction.
Page 499: Idle16
Miscellaneous Instruction Set Reference idle16 Syntax: IDLE16 ; Function: On the ADSP-21061 only, this instruction executes a NOP and puts the processor in a low power state. IDLE16 is a lower power version of the IDLE instruction. This instruction halts the processor like the IDLE instruction;...
Page 500: Cjump / Rframe
Miscellaneous Instruction Set Reference cjump / rframe Syntax: CJUMP function (DB) ; (PC, <reladdr24>) RFRAME ; Function: The CJUMP instruction is generated by the C compiler for function calls, and is not intended for use in assembly language programs. CJUMP combines a direct or PC-relative jump with register transfer operations that save the frame and stack pointers.
Page 501 Miscellaneous Instruction Set Reference cjump / rframe The ADDR field specifies a 24-bit program memory address for “function.” RELADDR is a 24-bit, twos-complement value that is added to the current PC value to generate the branch address. Opcode: (RFRAME) 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 0 0 0 1 1 0 0 1 0 0 0 0...
Page 502 Instruction Set Reference A – 56 www.BDTIC.com/ADI...
Page 503: B.1 Overview
Compute Operation Reference OVERVIEW Compute operations execute in the multiplier, the ALU and the shifter. The 23-bit compute field is like a mini-instruction within the ADSP-21000 instruction and can be specified for a variety of compute operations. This appendix describes each compute operation in detail, including its assembly language syntax and opcode field.
Page 504: B.2.1 Alu Operations
B Compute Operations The CU (computation unit) field is defined as follows: CU=00 ALU operations CU=01 Multiplier operations CU=10 Shifter operations In some shifter operations, data register RN is used both as a destination for a result operand and as source for a third input operand. The available operations and their 8-bit OPCODE values are listed in the following sections, organized by computation unit: ALU, multiplier and shifter.
Page 505: Table B.2 Floating-Point Alu Operations
Compute Operations Syntax Opcode Fn = Fx + Fy 1000 0001 Fn = Fx – Fy 1000 0010 Fn = ABS (Fx + Fy) 1001 0001 Fn = ABS (Fx – Fy) 1001 0010 Fn = (Fx + Fy)/2 1000 1001 COMP(Fx, Fy) 1000 1010 Fn = –Fx...
Page 506 ALU Fixed-Point B Compute Operations Rn = Rx + Ry Syntax: Rn = Rx + Ry Function: Adds the fixed-point fields in registers Rx and Ry. The result is placed in the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s.
Page 507 ALU Fixed-Point Compute Operations Rn = Rx – Ry Syntax: Rn = Rx – Ry Function: Subtracts the fixed-point field in register Ry from the fixed-point field in register Rx. The result is placed in the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s.
Page 508 ALU Fixed-Point B Compute Operations Rn = Rx + Ry + CI Syntax: Rn = Rx + Ry + CI Function: Adds with carry (AC from ASTAT) the fixed-point fields in registers Rx and Ry. The result is placed in the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s.
Page 509 ALU Fixed-Point Compute Operations Rn = Rx – Ry + CI – 1 Syntax: Rn = Rx – Ry + CI – 1 Function: Subtracts with borrow (AC – 1 from ASTAT) the fixed-point field in register Ry from the fixed-point field in register Rx. The result is placed in the fixed-point field in register Rn.
Page 510 ALU Fixed-Point B Compute Operations Rn = (Rx + Ry)/2 Syntax: Rn = (Rx + Ry)/2 Function: Adds the fixed-point fields in registers Rx and Ry and divides the result by 2. The result is placed in the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s.
Page 511: Comp(Rx, Ry)
ALU Fixed-Point Compute Operations COMP(Rx, Ry) Syntax: COMP(Rx, Ry) Function: Compares the fixed-point field in register Rx with the fixed-point field in register Ry. Sets the AZ flag if the two operands are equal, and the AN flag if the operand in register Rx is smaller than the operand in register The ASTAT register stores the results of the previous eight ALU compare operations in bits 24-31.
Page 512 ALU Fixed-Point B Compute Operations Rn = Rx + CI Syntax: Rn = Rx + CI Function: Adds the fixed-point field in register Rx with the carry flag from the ASTAT register (AC). The result is placed in the fixed-point field in register Rn.
Page 513 ALU Fixed-Point Compute Operations Rn = Rx + CI – 1 Syntax: Rn = Rx + CI – 1 Function: Adds the fixed-point field in register Rx with the borrow from the ASTAT register (AC – 1). The result is placed in the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s.
Page 514 ALU Fixed-Point B Compute Operations Rn = Rx + 1 Syntax: Rn = Rx + 1 Function: Increments the fixed-point operand in register Rx. The result is placed in the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s.
Page 515 ALU Fixed-Point Compute Operations Rn = Rx – 1 Syntax: Rn = Rx – 1 Function: Decrements the fixed-point operand in register Rx. The result is placed in the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s.
Page 516: Rn = –Rx
ALU Fixed-Point B Compute Operations Rn = –Rx Syntax: Rn = –Rx Function: Negates the fixed-point operand in Rx by twos complement. The result is placed in the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s. Negation of the minimum negative number (0x8000 0000) causes an overflow.
Page 517 ALU Fixed-Point Compute Operations Rn = ABS Rx Syntax: Rn = ABS Rx Function: Determines the absolute value of the fixed-point operand in Rx. The result is placed in the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s. ABS of the minimum negative number (0x8000 0000) causes an overflow.
Page 518 ALU Fixed-Point B Compute Operations Rn = PASS Rx Syntax: Rn = PASS Rx Function: Passes the fixed-point operand in Rx through the ALU to the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s. Status flags: Is set if the fixed-point output is all 0s, otherwise cleared AU Is cleared...
Page 519 ALU Fixed-Point Compute Operations Rn = Rx AND Ry Syntax: Rn = Rx AND Ry Function: Logically ANDs the fixed-point operands in Rx and Ry. The result is placed in the fixed-point field in Rn. The floating-point extension field in Rn is set to all 0s.
Page 520 ALU Fixed-Point B Compute Operations Rn = Rx OR Ry Syntax: Rn = Rx OR Ry Function: Logically ORs the fixed-point operands in Rx and Ry. The result is placed in the fixed-point field in Rn. The floating-point extension field in Rn is set to all 0s.
Page 521 ALU Fixed-Point Compute Operations Rn = Rx XOR Ry Syntax: Rn = Rx XOR Ry Function: Logically XORs the fixed-point operands in Rx and Ry. The result is placed in the fixed-point field in Rn. The floating-point extension field in Rn is set to all 0s.
Page 522 ALU Fixed-Point B Compute Operations Rn = NOT Rx Syntax: Rn = NOT Rx Function: Logically complements the fixed-point operand in Rx. The result is placed in the fixed-point field in Rn. The floating-point extension field in Rn is set to all 0s.
Page 523: Rn = Min(Rx, Ry)
ALU Fixed-Point Compute Operations Rn = MIN(Rx, Ry) Syntax: Rn = MIN(Rx, Ry) Function: Returns the smaller of the two fixed-point operands in Rx and Ry. The result is placed in the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s. Status flags: Is set if the fixed-point output is all 0s, otherwise cleared AU Is cleared...
Page 524: Rn = Max(Rx, Ry)
ALU Fixed-Point B Compute Operations Rn = MAX(Rx, Ry) Syntax: Rn = MAX(Rx, Ry) Function: Returns the larger of the two fixed-point operands in Rx and Ry. The result is placed in the fixed-point field in register Rn. The floating-point extension field in Rn is set to all 0s.
Page 525 ALU Fixed-Point Compute Operations Rn = CLIP Rx BY Ry Syntax: Rn = CLIP Rx BY Ry Function: Returns the fixed-point operand in Rx if the absolute value of the operand in Rx is less than the absolute value of the fixed-point operand in Ry. Otherwise, returns |Ry| if Rx is positive, and –|Ry| if Rx is negative.
Page 526 ALU Floating-Point B Compute Operations Fn = Fx + Fy Syntax: Fn = Fx + Fy Function: Adds the floating-point operands in registers Fx and Fy. The normalized result is placed in register Fn. Rounding is to nearest (IEEE) or by truncation, to a 32-bit or to a 40-bit boundary, as defined by the rounding mode and rounding boundary bits in MODE1.
Page 527 ALU Floating-Point Compute Operations Fn = Fx – Fy Syntax: Fn = Fx – Fy Function: Subtracts the floating-point operand in register Fy from the floating-point operand in register Fx. The normalized result is placed in register Fn. Rounding is to nearest (IEEE) or by truncation, to a 32-bit or to a 40-bit boundary, as defined by the rounding mode and rounding boundary bits in MODE1.
Page 528 ALU Floating-Point B Compute Operations Fn = ABS (Fx + Fy) Syntax: Fn = ABS (Fx + Fy) Function: Adds the floating-point operands in registers Fx and Fy, and places the absolute value of the normalized result in register Fn. Rounding is to nearest (IEEE) or by truncation, to a 32-bit or to a 40-bit boundary, as defined by the rounding mode and rounding boundary bits in MODE1.
Page 529 ALU Floating-Point Compute Operations Fn = ABS (Fx – Fy) Syntax: Fn = ABS (Fx – Fy) Function: Subtracts the floating-point operand in Fy from the floating-point operand in Fx and places the absolute value of the normalized result in register Fn. Rounding is to nearest (IEEE) or by truncation, to a 32-bit or to a 40-bit boundary, as defined by the rounding mode and rounding boundary bits in MODE1.
Page 530 ALU Floating-Point B Compute Operations Fn = (Fx + Fy)/2 Syntax: Fn = (Fx + Fy)/2 Function: Adds the floating-point operands in registers Fx and Fy and divides the result by 2, by decrementing the exponent of the sum before rounding. The normalized result is placed in register Fn.
Page 531: Comp(Fx, Fy)
ALU Floating-Point Compute Operations COMP(Fx, Fy) Syntax: COMP(Fx, Fy) Function: Compares the floating-point operand in register Fx with the floating-point operand in register Fy. Sets the AZ flag if the two operands are equal, and the AN flag if the operand in register Fx is smaller than the operand in register Fy.
Page 532: Fn = –Fx
ALU Floating-Point B Compute Operations Fn = –Fx Syntax: Fn = –Fx Function: Complements the sign bit of the floating-point operand in Fx. The complemented result is placed in register Fn. A denormal input is flushed to ±Zero. A NAN input returns an all 1s result. Status flags: Is set if the result operand is a ±Zero, otherwise cleared AU Is cleared...
Page 533 ALU Floating-Point Compute Operations Fn = ABS Fx Syntax: Fn = ABS Fx Function: Returns the absolute value of the floating-point operand in register Fx by setting the sign bit of the operand to 0. Denormal inputs are flushed to +Zero.
Page 534 ALU Floating-Point B Compute Operations Fn = PASS Fx Syntax: Fn = PASS Fx Function: Passes the floating-point operand in Fx through the ALU to the floating- point field in register Fn. Denormal inputs are flushed to ±Zero. A NAN input returns an all 1s result.
Page 535 ALU Floating-Point Compute Operations Fn = RND Fx Syntax: Fn = RND Fx Function: Rounds the floating-point operand in register Fx to a 32 bit boundary. Rounding is to nearest (IEEE) or by truncation, as defined by the rounding mode bit in MODE1. Post-rounded overflow returns ±Infinity (round-to- nearest) or ±NORM.MAX (round-to-zero).
Page 536 ALU Floating-Point B Compute Operations Fn = SCALB Fx BY Ry Syntax: Fn = SCALB Fx BY Ry Function: Scales the exponent of the floating-point operand in Fx by adding to it the fixed-point twos-complement integer in Ry. The scaled floating-point result is placed in register Fn.
Page 537 ALU Floating-Point Compute Operations Rn = MANT Fx Syntax: Rn = MANT Fx Function: Extracts the mantissa (fraction bits with explicit hidden bit, excluding the sign bit) from the floating-point operand in Fx. The unsigned-magnitude result is left-justified (1.31 format) in the fixed-point field in Rn. Rounding modes are ignored and no rounding is performed because all results are inherently exact.
Page 538 ALU Floating-Point B Compute Operations Rn = LOGB Fx Syntax: Rn = LOGB Fx Function: Converts the exponent of the floating-point operand in register Fx to an unbiased twos-complement fixed-point integer. The result is placed in the fixed-point field in register Rn. Unbiasing is done by subtracting 127 from the floating-point exponent in Fx.
Page 539 ALU Floating-Point Compute Operations Rn = FIX Fx Rn = TRUNC Fx Syntax: Rn = FIX Fx Rn = TRUNC Fx Rn = FIX Fx BY Ry Rn = TRUNC Fx BY Ry Function: Converts the floating-point operand in Fx to a twos-complement 32-bit fixed-point integer result.
Page 540 ALU Floating-Point B Compute Operations Fn = FLOAT Rx BY Ry / Fn = FLOAT Rx Syntax: Fn = FLOAT Rx BY Ry Fn = FLOAT Rx Function: Converts the fixed-point operand in Rx to a floating-point result. If a scaling factor (Ry) is specified, the fixed-point twos-complement integer in Ry is added to the exponent of the floating-point result.
Page 541: Fn = Recips Fx
ALU Floating-Point Compute Operations Fn = RECIPS Fx Syntax: Fn = RECIPS Fx Function: Creates an 8-bit accurate seed for 1/Fx, the reciprocal of Fx. The mantissa of the seed is determined from a ROM table using the 7 MSBs (excluding the hidden bit) of the Fx mantissa as an index.
Page 542: Fn = Rsqrts Fx
ALU Floating-Point B Compute Operations Fn = RSQRTS Fx Syntax: Fn = RSQRTS Fx Function: Creates a 4-bit accurate seed for 1/√Fx, the reciprocal square root of Fx. The mantissa of the seed is determined from a ROM table using the LSB of the biased exponent of Fx concatenated with the 6 MSBs (excluding the hidden bit) of the mantissa of Fx as an index.
Page 543: Fn = Fx Copysign Fy
ALU Floating-Point Compute Operations Fn = Fx COPYSIGN Fy Syntax: Fn = Fx COPYSIGN Fy Function: Copies the sign of the floating-point operand in register Fy to the floating- point operand from register Fx without changing the exponent or the mantissa.
Page 544: Fn = Min(Fx, Fy)
ALU Floating-Point B Compute Operations Fn = MIN(Fx, Fy) Syntax: Fn = MIN(Fx, Fy) Function: Returns the smaller of the floating-point operands in register Fx and Fy. A NAN input returns an all 1s result. MIN of +Zero and –Zero returns –Zero.
Page 545: Fn = Max(Fx, Fy)
ALU Floating-Point Compute Operations Fn = MAX(Fx, Fy) Syntax: Fn = MAX(Fx, Fy) Function: Returns the larger of the floating-point operands in registers Fx and Fy. A NAN input returns an all 1s result. MAX of +Zero and –Zero returns +Zero.
Page 546 ALU Floating-Point B Compute Operations Fn = CLIP Fx BY Fy Syntax: Fn = CLIP Fx BY Fy Function: Returns the floating-point operand in Fx if the absolute value of the operand in Fx is less than the absolute value of the floating-point operand in Fy.
Page 547: B.2.2 Multiplier Operations
Compute Operations B.2.2 Multiplier Operations The multiplier operations are described in this section. Table B.3 summarizes the syntax and opcodes for the fixed-point and floating-point multiplier operations. The rest of this section contains detailed descriptions of each operation. Fixed-point: Syntax Opcode †...
Page 548: Table B.4 Multiplier Mod2 Options
B Compute Operations Mod2 in Table B.3 is an optional modifier, enclosed in parentheses, consisting of three or four letters that indicate whether the x-input is signed (S) or unsigned (U), whether the y-input is signed or unsigned, whether the inputs are in integer (I) or fractional (F) format and whether the result when written to the register file is to be rounded-to-nearest (R).
Page 549 Multiplier Fixed-Point Compute Operations Rn|MR = Rx * Ry Syntax: = Rx * Ry mod2 = Rx * Ry mod2 = Rx * Ry mod2 Function: Multiplies the fixed-point fields in registers Rx and Ry. If rounding is specified (fractional data only), the result is rounded. The result is placed either in the fixed-point field in register Rn or one of the MR accumulation registers.
Page 550 Multiplier Fixed-Point B Compute Operations Rn|MR = MR + Rx * Ry Syntax: = MRF + Rx * Ry mod2 = MRB + Rx * Ry mod2 = MRF + Rx * Ry mod2 = MRB + Rx * Ry mod2 Function: Multiplies the fixed-point fields in registers Rx and Ry, and adds the product to the specified MR register value.
Page 551 Multiplier Fixed-Point Compute Operations Rn|MR = MR – Rx * Ry Syntax: = MRF – Rx * Ry mod2 = MRB – Rx * Ry mod2 = MRF – Rx * Ry mod2 = MRB – Rx * Ry mod2 Function: Multiplies the fixed-point fields in registers Rx and Ry, and subtracts the product from the specified MR register value.
Page 552: Rn|Mr = Sat Mr
Multiplier Fixed-Point B Compute Operations Rn|MR = SAT MR Syntax: = SAT MRF mod1 = SAT MRB mod1 = SAT MRF mod1 = SAT MRB mod1 Function: If the value of the specified MR register is greater than the maximum value for the specified data format, the multiplier sets the result to the maximum value.
Page 553: Rn|Mr = Rnd Mr
Multiplier Fixed-Point Compute Operations Rn|MR = RND MR Syntax: = RND MRF mod1 = RND MRB mod1 = RND MRF mod1 = RND MRB mod1 Function: Rounds the specified MR value to nearest at bit 32 (the MR1-MR0 boundary). The result is placed either in the fixed-point field in register Rn or one of the MR accumulation registers, which must be the same MR register that provided the input.
Page 554: Mr=Rn / Rn=Mr
Multiplier Fixed-Point Multiplier Fixed-Point B Compute Operations MR=0 MR=Rn / Rn=MR Syntax: MRF = 0 MRB = 0 Function: Sets the value of the specified MR register to zero. All 80 bits (MR2, MR1, MR0) are cleared. Status flags: MN Is cleared Is cleared MU Is cleared Is cleared...
Page 555 Multiplier Floating-Point Compute Operations Fn = Fx * Fy Syntax: Fn = Fx * Fy Function: Multiplies the floating-point operands in registers Fx and Fy. The result is placed in the register Fn. Status flags: MN Is set if the result is negative, otherwise cleared MV Is set if the unbiased exponent of the result is greater than 127, otherwise cleared MU Is set if the unbiased exponent of the result is less than –126,...
Page 556: B.2.3 Shifter Operations
B Compute Operations B.2.3 Shifter Operations Shifter operations are described in this section. Table B.6 summarizes the syntax and opcodes for the shifter operations. The succeeding pages provide detailed descriptions of each operation. The shifter operates on the register file’s 32-bit fixed-point fields (bits 39- 8).
Page 557: Rn = Lshift Rx By Ry|
Shifter Compute Operations Rn = LSHIFT Rx BY Ry|<data8> Syntax: Rn = LSHIFT Rx BY Ry Rn = LSHIFT Rx BY <data8> Function: Logically shifts the fixed-point operand in register Rx by the 32-bit value in register Ry or by the 8-bit immediate value in the instruction. The shifted result is placed in the fixed-point field of register Rn.
Page 558: Rn = Rn Or Lshift Rx By Ry|
Shifter B Compute Operations Rn = Rn OR LSHIFT Rx BY Ry|<data8> Syntax: Rn = Rn OR LSHIFT Rx BY Ry Rn = Rn OR LSHIFT Rx BY <data8> Function: Logically shifts the fixed-point operand in register Rx by the 32-bit value in register Ry or by the 8-bit immediate value in the instruction.
Page 559: Rn = Ashift Rx By Ry|
Shifter Compute Operations Rn = ASHIFT Rx BY Ry|<data8> Syntax: Rn = ASHIFT Rx BY Ry Rn = ASHIFT Rx BY <data8> Function: Arithmetically shifts the fixed-point operand in register Rx by the 32-bit value in register Ry or by the 8-bit immediate value in the instruction. The shifted result is placed in the fixed-point field of register Rn.
Page 560: Rn = Rn Or Ashift Rx By Ry|
Shifter B Compute Operations Rn = Rn OR ASHIFT Rx BY Ry|<data8> Syntax: Rn = Rn OR ASHIFT Rx BY Ry Rn = Rn OR ASHIFT Rx BY <data8> Function: Arithmetically shifts the fixed-point operand in register Rx by the 32-bit value in register Ry or by the 8-bit immediate value in the instruction.
Page 561: Rn = Rot Rx By Ry|
Shifter Compute Operations Rn = ROT Rx BY Ry|<data8> Syntax: Rn = ROT Rx BY Ry Rn = ROT Rx BY <data8> Function: Rotates the fixed-point operand in register Rx by the 32-bit value in register Ry or by the 8-bit immediate value in the instruction. The rotated result is placed in the fixed-point field of register Rn.
Page 562: Rn = Bclr Rx By Ry|
Shifter B Compute Operations Rn = BCLR Rx BY Ry|<data8> Syntax: Rn = BCLR Rx BY Ry Rn = BCLR Rx BY <data8> Function: Clears a bit in the fixed-point operand in register Rx. The result is placed in the fixed-point field of register Rn. The floating-point extension field of Rn is set to all 0s.
Page 563: Rn = Bset Rx By Ry|
Shifter Compute Operations Rn = BSET Rx BY Ry|<data8> Syntax: Rn = BSET Rx BY Ry Rn = BSET Rx BY <data8> Function: Sets a bit in the fixed-point operand in register Rx. The result is placed in the fixed-point field of register Rn. The floating-point extension field of Rn is set to all 0s.
Page 564: Rn = Btgl Rx By Ry|
Shifter B Compute Operations Rn = BTGL Rx BY Ry|<data8> Syntax: Rn = BTGL Rx BY Ry Rn = BTGL Rx BY <data8> Function: Toggles a bit in the fixed-point operand in register Rx. The result is placed in the fixed-point field of register Rn. The floating-point extension field of Rn is set to all 0s.
Page 565: Btst Rx By Ry|
Shifter Compute Operations BTST Rx BY Ry|<data8> Syntax: BTST Rx BY Ry BTST Rx BY <data8> Function: Tests a bit in the fixed-point operand in register Rx. The SZ flag is set if the bit is a 0 and cleared if the bit is a 1. The position of the bit is the 32-bit value in register Ry or the 8-bit immediate value in the instruction.
Page 566: Rn = Fdep Rx By Ry|:
Shifter B Compute Operations Rn = FDEP Rx BY Ry|<bit6>:<len6> Syntax: Rn = FDEP Rx BY Ry Rn = FDEP Rx BY <bit6>:<len6> Function: Deposits a field from register Rx to register Rn. The input field is right-aligned within the fixed-point field of Rx. Its length is determined by the len6 field in register Ry or by the immediate len6 field in the instruction.
Page 567: Rn = Rn Or Fdep Rx By Ry|:
Shifter Compute Operations Rn = Rn OR FDEP Rx BY Ry|<bit6>:<len6> Syntax: Rn = Rn OR FDEP Rx BY Ry Rn = Rn OR FDEP Rx BY <bit6>:<len6> Function: Deposits a field from register Rx to register Rn. The field value is logically ORed bitwise with the specified field of register Rn and the new value is written back to register Rn.
Page 568: Rn = Fdep Rx By Ry|: (Se)
Shifter B Compute Operations Rn = FDEP Rx BY Ry|<bit6>:<len6> (SE) Syntax: Rn = FDEP Rx BY Ry (SE) Rn = FDEP Rx BY <bit6>:<len6> (SE) Function: Deposits and sign-extends a field from register Rx to register Rn. The input field is right-aligned within the fixed-point field of Rx.
Page 569: Rn = Rn Or Fdep Rx By Ry|: (Se)
Shifter Compute Operations Rn = Rn OR FDEP Rx BY Ry|<bit6>:<len6> (SE) Syntax: Rn = Rn OR FDEP Rx BY Ry (SE) Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE) Function: Deposits and sign-extends a field from register Rx to register Rn. The sign- extended field value is logically ORed bitwise with the value of register Rn and the new value is written back to register Rn.
Page 570: Rn = Fext Rx By Ry|:
Shifter B Compute Operations Rn = FEXT Rx BY Ry|<bit6>:<len6> Syntax: Rn = FEXT Rx BY Ry Rn = FEXT Rx BY <bit6>:<len6> Function: Extracts a field from register Rx to register Rn. The output field is placed right- aligned in the fixed-point field of Rn. Its length is determined by the len6 field in register Ry or by the immediate len6 field in the instruction.
Page 571: Rn = Fext Rx By Ry|: (Se)
Shifter Compute Operations Rn = FEXT Rx BY Ry|<bit6>:<len6> (SE) Syntax: Rn = FEXT Rx BY Ry (SE) Rn = FEXT Rx BY <bit6>:<len6> (SE) Function: Extracts and sign-extends a field from register Rx to register Rn. The output field is placed right-aligned in the fixed-point field of Rn.
Page 572 Shifter B Compute Operations Rn = EXP Rx Syntax: Rn = EXP Rx Function: Extracts the exponent of the fixed-point operand in Rx. The exponent is placed in the shf8 field in register Rn. The exponent is calculated as the twos complement of: # leading sign bits in Rx –...
Page 573 Shifter Compute Operations Rn = EXP Rx (EX) Syntax: Rn = EXP Rx (EX) Function: Extracts the exponent of the fixed-point operand in Rx, assuming that the operand is the result of an ALU operation. The exponent is placed in the shf8 field in register Rn.
Page 574 Shifter B Compute Operations Rn = LEFTZ Rx Syntax: Rn = LEFTZ Rx Function: Extracts the number of leading 0s from the fixed-point operand in Rx. The extracted number is placed in the bit6 field in Rn. Status flags: Is set if the MSB of Rx is 1, otherwise cleared Is set if the result is 32, otherwise cleared Is cleared B –...
Page 575 Shifter Compute Operations Rn = LEFTO Rx Syntax: Rn = LEFTO Rx Function: Extracts the number of leading 1s from the fixed-point operand in Rx. The extracted number is placed in the bit6 field in Rn. Status flags: Is set if the MSB of Rx is 0, otherwise cleared Is set if the result is 32, otherwise cleared Is cleared B –...
Page 576 Shifter B Compute Operations Rn = FPACK Fx Syntax: Rn = FPACK Fx Function: Converts the IEEE 32-bit floating-point value in Fx to a 16-bit floating- point value stored in Rn. The short float data format has an 11-bit mantissa with a four-bit exponent plus sign bit. The 16-bit floating-point numbers reside in the lower 16 bits of the 32-bit floating-point field.
Page 577: Fn = Funpack Rx
Shifter Compute Operations Fx = FUNPACK Rn Syntax: Fn = FUNPACK Rx Function: Converts the 16-bit floating-point value in Rx to an IEEE 32-bit floating- point value stored in Fx. The result of the FUNPACK operation is as follows: Condition Result 0 <...
Page 578: B.3 Multifunction Computations
B Compute Operations MULTIFUNCTION COMPUTATIONS Multifunction computations are of three types, each of which has a different format for the 23-bit compute field: • Dual add/subtract • Parallel multiplier/ALU • Parallel multiplier and add/subtract See “Multifunction Computations” in the Computation Units chapter for a summary of the multifunction operations.
Page 579: Dual Add/Subtract (Fixed-Pt.)
Multifunction Compute Operations Dual Add/Subtract (Fixed-Pt.) The dual add/subtract operation computes the sum and the difference of two inputs and returns the two results to different registers. There are fixed-point and floating-point versions of this operation. Fixed-Point: Syntax: Ra = Rx + Ry, Rs = Rx – Ry Compute Field: 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1...
Page 580: Dual Add/Subtract (Floating-Pt)
Multifunction B Compute Operations Dual Add/Subtract (Floating-Pt.) Floating-Point: Syntax: Fa = Fx + Fy, Fs = Fx – Fy Compute Field: 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 Function: Does a dual add/subtract of the floating-point operands in registers Fx...
Page 581: Parallel Multiplier & Alu (Fixed-Pt.)
Multifunction Compute Operations Parallel Multiplier & ALU (Fixed-Pt.) The parallel multiplier/ALU operation performs a multiply or multiply/accumulate and one of the following ALU operations: add, subtract, average, fixed-point to floating-point or floating-point to fixed- point conversion, or floating-point ABS, MIN or MAX. For detailed information about a particular operation, see the individual descriptions under Single-Function Operations.
Page 582: Parallel Multiplier & Alu (Floating-Pt.)
Multifunction B Compute Operations Parallel Multiplier & ALU (Floating-Pt.) Floating-Point: Syntax: See Table B.7 Compute Field: 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OPCODE The multiplier and ALU operations are determined by OPCODE.
Page 583: Table B.7 Parallel Multiplier/Alu Computations
Compute Operations Syntax Opcode Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12 000100 Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12 000101 Rm=R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2 000110 MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12 001000 MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 – R15-12 001001 MRF=MRF + R3-0 * R7-4 (SSF), Ra=(R11-8 + R15-12)/2 001010...
Page 584: Parallel Multiplier & Dual Add/Subtract
Multifunction B Compute Operations Parallel Multiplier & Dual Add/Subtract The parallel multiplier and dual add/subtract operation performs a multiply or multiply/accumulate and computes the sum and the difference of the ALU inputs. For detailed information on the multiplier operations, see the individual descriptions under Single-Function Operations.
Page 585 Multifunction Compute Operations Parallel Multiplier & Dual Add/Subtract The result operands can be returned to any registers within the register file. Each of the four input operands is restricted to a different set of four data registers. Input Allowed Sources Multiplier X: R3-R0 (F3-F0) Multiplier Y:...
Page 586 B Compute Operations B – 84 www.BDTIC.com/ADI...
Page 587: C.1 Overview
Numeric Formats OVERVIEW The ADSP-2106x supports the 32-bit single-precision floating-point data format defined in the IEEE Standard 754/854. In addition, the ADSP- 2106x supports an extended-precision version of the same format with eight additional bits in the mantissa (40 bits total). The ADSP-2106x also supports 32-bit fixed-point formats—fractional and integer—which can be signed (twos-complement) or unsigned.
Page 588: C.3 Extended Precision Floating-Point Format
C Numeric Formats The IEEE Standard also provides for several special data types in the single-precision floating-point format: • An exponent value of 255 (all ones) with a nonzero fraction is a Not-A- Number (NAN). NANs are usually used as flags for data flow control, for the values of uninitialized variables, and for the results of invalid operations such as 0 * ∞.
Page 589: C.4 Short Word Floating-Point Format
Numeric Formats SHORT WORD FLOATING-POINT FORMAT The ADSP-2106x supports a 16-bit floating-point data type and provides conversion instructions for it. The short float data format has an 11-bit mantissa with a four-bit exponent plus sign bit, as shown in Figure C.3. The 16-bit floating-point numbers reside in the lower 16 bits of the 32-bit floating-point field.
Page 590 C Numeric Formats FUNPACK Condition Result 0 < exp ≤ 15 Exponent is the 3 LSBs of the source exponent prefixed by the MSB of the source exponent and four copies of the complement of the MSB. The unpacked fraction is the source fraction with 12 zeros appended.
Page 591: C.5 Fixed-Point Formats
Numeric Formats FIXED-POINT FORMATS The ADSP-2106x supports two 32-bit fixed-point formats: fractional and integer. In both formats, numbers can be signed (twos-complement) or unsigned. The four possible combinations are shown in Figure C.4. In the fractional format, there is an implied binary point to the left of the most significant magnitude bit.
Page 592: Figure C.4 32-Bit Fixed-Point Formats
C Numeric Formats Signed Integer • • • Weight –2 • Sign Binary point Signed Fractional –1 –2 –29 –30 –31 • • • Weight –2 • Sign Binary point Unsigned Integer • • • Weight • Binary point Unsigned Fractional –1 –2 –3...
Page 593: Figure C.5 64-Bit Unsigned Fixed-Point Product
Numeric Formats • • • Weight Unsigned Integer –1 –2 –3 –62 –63 –64 • • • Weight Unsigned Fractional Figure C.5 64-Bit Unsigned Fixed-Point Product C – 7 www.BDTIC.com/ADI...
Page 594: Figure C.6 64-Bit Signed Fixed-Point Product
C Numeric Formats • • • Weight –2 Sign Signed Integer, No Left Shift –1 • • • Weight –2 Sign Signed Integer With Left Shift –1 –2 –61 –62 –63 • • • Weight –2 Sign Signed Fractional, No Left Shift –2 –3 –62...
Page 595: D.1 Overview
JTAG Test Access Port OVERVIEW A boundary scan allows a system designer to test interconnections on a printed circuit board with minimal test-specific hardware. The scan is made possible by the ability to control and monitor each input and output pin on each chip through a set of serially scannable latches.
Page 596: D.2 Test Access Port
(input) Test Reset. Resets the test state machine. Can be asynchronous with TCK. A BSDL file for the ADSP-2106x is available on Analog Devices’ BBS and Internet ftp site. The BBS can be reached at: (617) 461-4258 8 data bits, no parity, 1 stop bit,...
Page 597: D.3 Instruction Register
JTAG Test Access Port INSTRUCTION REGISTER The instruction register allows an instruction to be shifted into the processor. This instruction selects the test to be performed and/or the test data register to be accessed. The instruction register is 5 bits long with no parity bit.
Page 598: Figure D.1 Serial Scan Paths
D JTAG Test Access Port Boundary Register Bypass Register Instruction Register Figure D.1 Serial Scan Paths D – 4 www.BDTIC.com/ADI...
Page 599: D.4 Boundary Register
JTAG Test Access Port BOUNDARY REGISTER The Boundary register is 363 bits long. This section defines the latch type and function of each position in the scan path. The positions are numbered with 0 being the first bit output (closest to TDO) and 362 being the last (closest to TDI).
Page 600 D JTAG Test Access Port Scan Latch Signal Position Type Name output L3CLK (NC on the ADSP-21061) input L3CLK (NC on the ADSP-21061) output L3DAT0 (NC on the ADSP-21061) input L3DAT0 (NC on the ADSP-21061) output L3DAT1 (NC on the ADSP-21061) input L3DAT1 (NC on the ADSP-21061) output...
Page 601 JTAG Test Access Port Scan Latch Signal Position Type Name output L0DAT2 (NC on the ADSP-21061) input L0DAT2 (NC on the ADSP-21061) output L0DAT3 (NC on the ADSP-21061) input L0DAT3 (NC on the ADSP-21061) output enable L0ACK output enable (NC on the ADSP-21061) output enable L0DATx, L0CLK output enable (NC on the ADSP-21061) output...
Page 602 D JTAG Test Access Port Scan Latch Signal Position Type Name output DATA22 input DATA22 output DATA23 input DATA23 output DATA24 input DATA24 output DATA25 input DATA25 output DATA26 input DATA26 output enable DATAx output enable output DATA27 input DATA27 output DATA28 input...
Page 603 JTAG Test Access Port Scan Latch Signal Position Type Name input DATA45 output DATA46 input DATA46 output DATA47 input DATA47 output enable output enable output enable output enable output enable output enable output input output input output input output input output input output...
Page 604 D JTAG Test Access Port Scan Latch Signal Position Type Name output RCLK0 input RCLK0 input output TFS0 input TFS0 output TCLK0 input TCLK0 output output input output enable RFS1, output enable output enable RCLK1 output enable output enable TFS1 output enable output enable TCLK1 output enable output enable...
Page 605 JTAG Test Access Port Scan Latch Signal Position Type Name output ADDR27 input ADDR27 output ADDR26 input ADDR26 output ADDR25 input ADDR25 output ADDR24 input ADDR24 output ADDR23 input ADDR23 output ADDR22 input ADDR22 output ADDR21 input ADDR21 output ADDR20 input ADDR20 output...
Page 606 D JTAG Test Access Port Scan Latch Signal Position Type Name input ADDR3 output ADDR2 input ADDR2 output ADDR1 input ADDR1 output ADDR0 input ADDR0 output enable FLAG0 output enable output enable FLAG1 output enable output enable FLAG2 output enable output enable FLAG3 output enable output...
Page 607: D.5 Device Identification Register
JTAG Test Access Port DEVICE IDENTIFICATION REGISTER No device identification register is included in the ADSP-2106x. BUILT-IN SELF-TEST OPERATION (BIST) No self-test functions are supported by the ADSP-2106x. PRIVATE INSTRUCTIONS Loading a value of 001xx into the instruction register enables the private instructions reserved for emulation.
Page 608 D JTAG Test Access Port D – 14 www.BDTIC.com/ADI...
Page 609: E.1 Overview
Control/Status Registers OVERVIEW This appendix provides bit definitions for the ADSP-2106x’s control and status registers. Some of the registers are located in the processor core; these are called system registers, a subset of the processor’s universal register set. The core processor system registers are MODE1, MODE2, ASTAT, STKY, IRPTL, IMASK, IMASKP, USTAT1, and USTAT2.
Page 610: E.2 System Registers (Core Processor)
E Control/Status Registers All control and status bits are active high unless otherwise noted. Default bit values after reset are shown; if no value is shown, the bit is undefined at reset or depends upon processor inputs. Reserved bits are shown with a gray background.
Page 611: E.2.2 System Register Bit Operations
Control/Status Registers E.2.2 System Register Bit Operations The system register bit manipulation instruction can be used to set, clear, toggle, or test specific bits in the system registers. An immediate field in the bit manipulation instruction specifies the affected bits. This instruction is described in Appendix A, Instruction Set Reference, Group IV–...
Page 612: E.3 Iop Registers (I/O Processor)
E Control/Status Registers IOP REGISTERS (I/O PROCESSOR) The ADSP-2106x’s I/O Processor (IOP) registers are a separate set of memory-mapped control and data registers. The IOP registers are used to configure system-level functions including serial port I/O, link port I/O, and DMA transfers. I/O operations are handled by the ADSP-2106x’s on-chip I/O processor, independently from and transparent to the processor core.
Page 613: Table E.3 Iop Registers (System Control)
Control/Status Registers The IOP registers are arranged to allow a host processor (or other bus master) to easily access the most important registers by reading or writing to the smallest amount of memory. The host only needs to control a small number of address lines to access a set of 16, 32, or 64 IOP registers including SYSCON, SYSTAT, VIRPT, WAIT, MSGR0–MSGR7, and one or two full DMA channels.
Page 614: Table E.4 Iop Registers (Dma)
E Control/Status Registers Register Name(s) Width Description EPB0 External Port FIFO Buffer 0 EPB1 External Port FIFO Buffer 1 EPB2 External Port FIFO Buffer 2 EPB3 External Port FIFO Buffer 3 DMAC6 DMA Channel 6 Control Register (Ext. Port Buffer 0 or Link Buffer 4) 1, 2 DMAC7 DMA Channel 7 Control Register (Ext.
Page 615: Table E.5 Iop Registers (Link Ports)
Control/Status Registers Register Name Width Description LBUF0 48/32 Link Data Buffer 0 LBUF1 48/32 Link Data Buffer 1 LBUF2 48/32 Link Data Buffer 2 LBUF3 48/32 Link Data Buffer 3 LBUF4 48/32 Link Data Buffer 4 LBUF5 48/32 Link Data Buffer 5 LCTL Link Buffer Control Register LCOM...
Page 616: E.3.2 Iop Register Access Restrictions
E Control/Status Registers E.3.2 IOP Register Access Restrictions Because the IOP registers are memory-mapped they cannot be written with data coming directly from memory. They must instead be written from (or read into) ADSP-2106x core registers, usually one of the general-purpose registers of the register file (R15–R0).
Page 617: E.3.4 Iop Register Write Latencies
Control/Status Registers I/O bus IOP register accesses 3rd priority The bus with the highest priority will gain access to the IOP registers first and any lower priority accesses are held off (by extra cycles generated by the core processor and/or I/O processor). If a DMA grant has been given for an I/O access, that access will be completed before an access from any another bus is allowed.
Page 618 E Control/Status Registers Register Initialization Register Address Name After RESET Group Description 0x0000 SYSCON 0x0000 0010 SC System Configuration 0x0001 VIRPT 0x0002 0014 SC Multiprocessor Vector Interrupt 0x0002 WAIT 0x21AD 6B5A SC External Memory Wait State Configuration 0x0003 SYSTAT 0x0000 0nn0 * SC System Status 0x0004 EPB0...
Page 619: Table E.7 Iop Register Addresses, Reset Initialization, & Grouping
Control/Status Registers Register Initialization Register Address Name After RESET Group Description 0x0048 ni DA DMA Channel 7 Index (Ext. Port Buffer 1 or Link Buffer 5) 0x0049 ni DA DMA Channel 7 Modifier (Ext. Port Buffer 1 or Link Buffer 5) 0x004A ni DA DMA Channel 7 Count (Ext.
Page 620 E Control/Status Registers Register Initialization Register Address Name After RESET Group Description 0x0070 ni DA DMA Channel 2 Index (SPORT0 Transmit) 0x0071 ni DA DMA Channel 2 Modifier (SPORT0 Transmit) 0x0072 ni DA DMA Channel 2 Count (SPORT0 Transmit) 0x0073 ni DA DMA Channel 2 Chain Pointer (SPORT0 Transmit) 0x0074...
Page 621 Control/Status Registers Register Initialization Register Address Name After RESET Group Description 0x00F0 STCTL1 0x0000 0000 LSP SPORT1 Transmit Control Register 0x00F1 SRCTL1 0x0000 0000 LSP SPORT1 Receive Control Register 0x00F2 ni LSP SPORT1 Transmit Data Buffer 0x00F3 ni LSP SPORT1 Receive Data Buffer 0x00F4 TDIV1 ni LSP...
Page 622: E.4 Mode1 Register
E Control/Status Registers MODE1 REGISTER Name Definition Bit-reversing for I8 (DAG2) Bit-reversing for I0 (DAG1) SRCU Alternate register select for computation units SRD1H DAG1 alternate register select (7-4) SRD1L DAG1 alternate register select (3-0) SRD2H DAG2 alternate register select (15-12) SRD2L DAG2 alternate register select (11-8) SRRFH...
Page 623 Control/Status Registers E – 15 www.BDTIC.com/ADI...
Page 624: E.5 Mode2 Register
E Control/Status Registers master in a multiprocessor system. To enable the use of this condition, bits 17 and 18 of MODE1 must both be zeros; otherwise the condition is always evaluated as false. MODE2 REGISTER Name Definition IRQ0 1=edge sensitive; 0=level-sensitive IRQ0E IRQ1 1=edge sensitive;...
Page 625 Control/Status Registers 30 29 25 24 MODE2 FLG1O 0=FLAG1 Input 1=FLAG1 Output Processor ID FLG2O 0=FLAG2 Input Silicon Revision # 1=FLAG2 Output FLG3O 0=FLAG3 Input 1=FLAG3 Output CAFRZ 0=Cache Updates 1=Cache Freeze (No Updates) 15 14 0=FLAG0 Input FLG0O IRQ0E 0=IRQ0 Level-Sensitive 1=FLAG0 Output 1=IRQ0 Edge-Sensitive...
Page 626 E Control/Status Registers 28-29 Silicon revision # 30-31 Processor ID (ID=01 for ADSP-21060, ID=10 for ADSP-21062) ARITHMETIC STATUS REGISTER (ASTAT) Name Definition ALU result zero or floating-point underflow ALU overflow ALU result negative ALU fixed-point carry ALU X input sign (ABS and MANT operations) ALU floating-point invalid operation Multiplier result negative Multiplier overflow...
Page 627 Control/Status Registers ASTAT 25 24 CACC Compare Accumulation Shift Register Bit Test Flag for System Registers FLG3 FLG0 FLAG3 Value FLAG0 Value FLAG2 Value FLG2 FLG1 FLAG1 Value 15 14 ALU Zero/Floating-Point Underflow Shifter Input Sign ALU Overflow Shifter Zero ALU Negative Shifter Overflow ALU Fixed-Point Carry...
Page 628: E.7 Sticky Status (Stky)
E Control/Status Registers STICKY STATUS (STKY) Name Definition ALU floating-point underflow ALU floating-point overflow ALU fixed-point overflow reserved ALU floating-point invalid operation Multiplier fixed-point overflow Multiplier floating-point overflow Multiplier floating-point underflow Multiplier floating-point invalid operation 10-16 reserved CB7S DAG1 circular buffer 7 overflow CB15S DAG2 circular buffer 15 overflow 19-20...
Page 629 Control/Status Registers STKY CB7S DAG1 Circular Buffer 7 Overflow Loop Stack Empty (read-only) LSEM CB15S DAG2 Circular Buffer 15 Overflow Loop Stack Overflow (read-only) LSOV Status Stack Empty (read-only) SSEM PCFL PC Stack Full (read-only) Status Stack Overflow (read-only) SSOV PCEM PC Stack Empty (read-only) NS - Not Sticky...
Page 630: E.8 Interrupt Latch (Irptl) & Interrupt Mask Imask)
E Control/Status Registers INTERRUPT LATCH (IRPTL) & INTERRUPT MASK (IMASK) IRPTL and IMASK have the exact same bit positions, corresponding to the ADSP-2106x interrupts in order of priority. Vector Interrupt Address* Name Function 0x00 – reserved 0x04 RSTI Reset (read-only)** HIGHEST PRIORITY 0x08 –...
Page 631 Control/Status Registers IRPTL & IMASK 30 29 SFT3I EP0I User Software Interrupt 3 Ext. Port Buffer 0 (or Link Buffer 4) DMA SFT2I EP1I User Software Interrupt 2 Ext. Port Buffer 1 (or Link Buffer 5) DMA SFT1I EP2I User Software Interrupt 1 Ext.
Page 632: E.9 System Configuration (Syscon)
E Control/Status Registers SYSTEM CONFIGURATION (SYSCON) The SYSCON register is used to set up system configuration selections. SYSCON is memory-mapped in internal memory at address 0x0000. After reset the SYSCON register is initialized to 0x0000 0010. This causes the ADSP-2106x to assume a 16-bit bus for any host processor; two 16-bit words must be written to SYSCON to change the setting of HPM, even if the host bus is 32 bits wide.
Page 633 Control/Status Registers 25 24 SYSCON 0x0000 IMGR EBPR Internal Memory Grouping External Bus Priority (for mesh multiprocessing) 00=even, 01=core processor, 10=I/O processor DCPR DMA Channel 6-9 Priority 1 = rotating, 0 = sequential 15 14 SRST Software Reset MSIZE External Memory Bank Size Boot Select Override MSIZE = log 2 (bank size) –...
Page 634 E Control/Status Registers Instruction Word Transfer—Specifies the word width for direct reads and direct writes of the ADSP-2106x’s internal memory (by other ADSP-2106xs or by the host). IWT=1 overrides the IMDW bits (see below) and forces a 48-bit (3-column) memory transfer. IWT=0 defers to the data word setting of the IMDW bits in the SYSCON register.
Page 635 Control/Status Registers To change the host packing mode, the following sequence must occur: 1. Write to the SYSCON register, changing the setting of HPM. 2. Read SYSCON (and ignore data) to ensure that the write was completed. 3. Repeat the write to SYSCON (to flush the read, since it may have occurred in the old packing mode).
Page 636 E Control/Status Registers Buffer Hang Disable—Disables the hang condition that occurs when the ADSP-2106x core tries to read from an empty (or write to a full) SPORT buffer (RX/TX), link port buffer (LBUFx), or external port buffer (EPBx). The hang condition also occurs when an external device—either another ADSP-2106x or a host processor—tries to read from an empty buffer or write to a full buffer.
Page 637: E.10 System Status (Systat)
Control/Status Registers Note: The setting of EPBR is not related to the CPA pin function (core priority access). (Additional Details: The ADSP-2106x has three on-chip buses that are multiplexed at the external port: the PM bus (instructions or data), DM bus (data), and I/O bus (DMA data). The PM bus and DM bus are controlled by the ADSP-2106x processor core.
Page 638 E Control/Status Registers memory at address 0x0003. After reset, all bits in SYSTAT are initialized to zero except for IDC(2:0) and CRBM(2:0). IDC(2:0) will be equal to the value of the ADSP-2106x’s ID inputs. CRBM(2:0) is equal to the ID of the current bus master, for ID>0.
Page 639 Control/Status Registers SYSTAT 30 29 0x0003 15 14 HSTM Host Mastership BSYN Bus Synchronization CRBM Current Bus Master ID Code DWPD Direct Write Pending VIPD Vector Interrupt Pending Host Packing Status 00 = packing complete 01 = first stage of all packing and unpacking modes 10 = second stage of 16-to-48 bit packing/unpacking or 32-to-48 bit packing/unpacking All control and status bits are active high unless otherwise noted.
Page 640 E Control/Status Registers 01=First stage of all packing and unpacking modes. 10=Second stage of 16-to-48 bit packing/unpacking or 32-to-48 bit packing/unpacking E.11 EXTERNAL MEMORY WAIT STATE CONTROL (WAIT) The WAIT register is used to set up external memory wait states and response to the ACK signal.
Page 641 Control/Status Registers Bus Idle Cycle – inactive bus cycle automatically generated Number of Wait States to avoid bus driver conflicts; devices with slow disable # of Hold times should enable bus idle cycle generation by using # of Wait Idle Time wait states code 001, 010, or 011.
Page 642 E Control/Status Registers E.12 EXTERNAL PORT DMA CONTROL (DMAC6-DMAC9) The DMAC6, DMAC7, DMAC8, and DMAC9 registers on the ADSP-21060 and ADSP-21062 are used to control external port DMA operations on DMA channels 6, 7, 8, and 9. (On the ADSP-21061, only DMAC6 and DMAC7 are available.) These registers are memory-mapped at internal memory addresses 0x001C, 0x001D, 0x001E, and 0x001F, respectively.
Page 643 Control/Status Registers DMAC6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0x001C DMAC7 0x001D DMAC8 0x001E DMAC9 0x001F 15 14 13 12 11 10 9 DMA Enable for Ext. Port Ext. Port FIFO Buffer Status 1=enable, 0=disable 00=empty, 10=partially full, 11=full CHEN...
Page 644 E Control/Status Registers DTYPE Data Type—Specifies the type of data being transferred; this information is used by internal memory to determine the word width. DTYPE=1 overrides the IMDW bits and forces a 48-bit (3- column) memory transfer. DTYPE=0 defers to the data word setting of the IMDW bits in the SYSCON register.
Page 645 Control/Status Registers added latency of the FLSH bit, it should not be set in the same DMACx write in which the DEN bit is set. As a general rule, set FLSH at least one cycle before setting any other DMACx control bits. EPBx Buffer Status—FS is a two-bit status field that indicates whether data is present in the EPBx buffer.
Page 646 E Control/Status Registers The MASTER, HSHAKE, and EXTERN bits are used in combination to provide the following DMA transfer modes: M H E DMA Mode of Operation Slave Mode. The DMA request is generated whenever the receive buffer is not empty or the transmit buffer is not full. Reserved Handshake Mode.
Page 647: E.13 Dma Channel Status (Dmastat)
Control/Status Registers E.13 DMA CHANNEL STATUS (DMASTAT) The DMASTAT register maintains status bits for each DMA channel. This register is memory-mapped at internal memory addresses 0x0037. For a particular channel, the channel active status bit will be set if DMA is enabled and the current DMA sequence has not completed.
Page 648 E Control/Status Registers DMASTAT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x0037 Channel 6 Chaining Status Channel 7 Chaining Status Channel 8 Chaining Status Channel 9 Chaining Status 15 14 13 12 11 10 9 Channel 5 Chaining Status Channel 0 Status...
Page 649: E.14 Link Buffer Control (Lctl)
Control/Status Registers E.14 LINK BUFFER CONTROL (LCTL) LCTL is the main control register for the six link port data buffers (LBUF0-5). [This register is not available on the ADSP-21061.] The LCTL register contains control bits unique to each link buffer. LCTL is memory- mapped at address 0x00C6.
Page 650 E Control/Status Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LCTL 0x00C6 LEXT5 L4EN LBUF5 Extended Word Size 1=48-bit transfers LBUF4 Enable 0=32-bit transfers L4DEN LEXT4 LBUF4 DMA Enable LBUF4 Extended Word Size L4CHEN 1=48-bit transfers LBUF4 Chained DMA Enable...
Page 651: E.15 Link Buffer Common Control (Lcom)
Control/Status Registers E.15 LINK BUFFER COMMON CONTROL (LCOM) The LCOM register contains status bits for each buffer, functions common to all links, and mesh multiprocessing functions. [This register is not available on the ADSP-21061.] LCOM is memory- mapped at address 0x00C7. After reset, LCOM is cleared (initialized to 0x0000 0000).
Page 652 E Control/Status Registers LCOM 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0x00C7 LRERR5 LCLKX24 Rcv. Pack Error Status for Link Buffer 5 Transfer at 2x Clock Rate 1=incomplete, 0=complete on Link Buffer 4 LRERR4 LCLKX25 Rcv.
Page 653 Control/Status Registers LxSTAT(0:1) Link Buffer Status—When transmitting, these status bits indicate whether there is room in the buffer for more data. When receiving, these status bits indicate whether new (unread) data is available in the receive buffer. LxSTAT(1)=1 if there is data in the buffer.
Page 654: E.16 Link Assignment Register (Lar)
E Control/Status Registers E.16 LINK ASSIGNMENT REGISTER (LAR) The LAR register is used to select link port to link buffer connections. LAR is memory-mapped at address 0x00C8. [This register is not available on the ADSP-21061.] After reset LAR is initialized to 0x0002 C688, assigning Link Port 0 to Link Buffer 0, Link Port 1 to Link Buffer 1, Link Port 2 to Link Buffer 2, Link Port 3 to Link Buffer 3, Link Port 4 to Link Buffer 4, and Link Port 5 to Link Buffer 5.
Page 655: E.17 Link Service Request (Lsrq)
Control/Status Registers E.17 LINK SERVICE REQUEST (LSRQ) The LSRQ register indicates when a disabled link port is accessed from an external source. It also contains mask bits for these interrupts. [This register is not available on the ADSP-21061.] LSRQ is memory-mapped at address 0x00C9.
Page 656 E Control/Status Registers LSRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0x00C9 L5RRQ L0TRQ Link Port 5 Receive Request Link Port 0 Transmit Request L5TRQ L0RRQ Link Port 5 Transmit Request Link Port 0 Receive Request L4RRQ L1TRQ...
Page 657 Control/Status Registers E.18 SPORT TRANSMIT CONTROL (STCTL0, STCTL1) STCTL0 and STCTL1 are the transmit control registers for SPORT0 and SPORT1 respectively. STCTL0 is memory-mapped at address 0x00E0, and STCTL1 is memory-mapped at address 0x00F0. After reset, these registers are cleared (initialized to 0x0000 0000). When changing TX Data Buffer S 11=full, 00=empty operating modes, a serial port control register should be cleared...
Page 658 E Control/Status Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 STCTL0 0x00E0 STCTL1 0x00F0 LRFS Active Low RFS RX Data Buffer Status (read-only) 1=active low, 0=active high 11=full, 00=empty, 10=partially full LAFS* ROVF Late RFS Receive Overflow Status (sticky, read-only)
Page 659: E.19 Sport Receive Control (Srctl0, Srctl1)
Control/Status Registers E.19 SPORT RECEIVE CONTROL (SRCTL0, SRCTL1) SRCTL0 and SRCTL1 are the transmit control registers for SPORT0 and SPORT1 respectively. SRCTL0 is memory-mapped at address 0x00E1 and SRCTL1 is memory-mapped at address 0x00F1. After reset, these registers are cleared (initialized to 0x0000 0000). When changing operating modes, a serial port control register should be cleared (i.e.
Page 660 E Control/Status Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SRCTL0 0x00E1 SRCTL1 0x00F1 LRFS Active Low RFS RX Data Buffer Status (read-only) 1=active low, 0=active high 11=full, 00=empty, 10=partially full LAFS* ROVF Late RFS Receive Overflow Status (sticky, read-only)
Page 661: E.20 Sport Divisors (Tdiv, Rdiv)
Control/Status Registers E.20 SPORT DIVISORS (TDIV, RDIV) 0x00E1 The TDIV0, TDIV1, RDIV0, and RDIV1 registers contain divisor values 0x00F1 that determine the frequencies for internally generated serial port clocks and frame syncs. These four registers are memory-mapped at addresses 0x00E4, 0x00F4, 0x00E6, and 0x00F6 respectively. These registers are not initialized after reset.
Page 662: E.21 Symbol Definitions File (Def21060.H)
E Control/Status Registers E.21 SYMBOL DEFINITIONS FILE (def21060.h) The IOP registers are programmed by writing to the appropriate address in memory. The symbolic names of the registers and individual bits can be used in ADSP-2106x programs—the #define definitions for these symbols are contained in the file def21060.h which is provided in the INCLUDE directory of the ADSP-21000 Family Development Software.
Page 663 Control/Status Registers /* MODE2 register */ #define IRQ0E 0x00000001 /* Bit 0: IRQ0- 1=edge sens. 0=level sens. */ #define IRQ1E 0x00000002 /* Bit 1: IRQ1- 1=edge sens. 0=level sens. */ #define IRQ2E 0x00000004 /* Bit 2: IRQ2- 1=edge sens. 0=level sens. */ #define CADIS 0x00000010 /* Bit 4: Cache disable...
Page 664 E Control/Status Registers /* STKY register */ #define AUS 0x00000001 /* Bit 0: ALU fltg-pt. underflow #define AVS 0x00000002 /* Bit 1: ALU fltg-pt. overflow #define AOS 0x00000004 /* Bit 2: ALU fixed-pt. overflow #define AIS 0x00000020 /* Bit 5: ALU fltg-pt. invalid operation #define MOS 0x00000040 /* Bit 6: Multiplier fixed-pt.
Page 665 Control/Status Registers /* I/O Processor Registers */ #define SYSCON 0x00 /* System configuration register #define VIRPT 0x01 /* Vector interrupt register #define WAIT 0x02 /* Wait state configuration for ext. memory */ #define SYSTAT 0x03 /* System status register #define EPB0 0x04 /* External port DMA buffer 0 #define EPB1...
Page 666 E Control/Status Registers #define EC6 0x47 /* External DMA6 counter #define II7 0x48 /* Internal DMA7 memory address #define IM7 0x49 /* Internal DMA7 memory access modifier #define C7 0x4a /* Contains number of DMA7 transfers remaining */ #define CP7 0x4b /* Points to next DMA7 parameters #define GP7...
Page 667 Control/Status Registers #define GP1 0x6c /* DMA1 General purpose / 2-D DMA #define DB1 0x6d /* DMA1 General purpose / 2-D DMA, not on 21061 */ #define DA1 0x6e /* DMA1 General purpose / 2-D DMA, not on 21061 */ #define II3 0x78 /* Internal DMA3 memory address...
Page 668 E Control/Status Registers #define STCTL1 0xf0 /*SPORT1 Transmit Control Register #define SRCTL1 0xf1 /*SPORT1 Receive Control Register #define TX1 0xf2 /*SPORT1 Transmit Data Buffer #define RX1 0xf3 /*SPORT1 Receive Data Buffer #define TDIV1 0xf4 /*SPORT1 Transmit Divisor #define TCNT1 0xf5 /*SPORT1 Transmit Count Reg #define RDIV1 0xf6 /*SPORT1 Receive Divisor #define RCNT1...
Page 669: Interrupt Vector Addresses
Interrupt Vector Addresses IRPTL/ IMASK Vector Interrupt Bit # Address* Name** Function 0x00 – reserved 0x04 RSTI Reset (read-only, non-maskable) HIGHEST PRIORITY 0x08 – reserved 0x0C SOVFI Status stack or loop stack overflow or PC stack full 0x10 TMZHI Timer=0 (high priority option) 0x14 VIRPTI Vector Interrupt...
Page 670 F Interrupt Vector Addresses Table F.1 shows all ADSP-2106x interrupts, listed according their bit position in the IRPTL and IMASK registers. Also shown is the address of the interrupt vector; each vector is separated by eight memory locations. The addresses in the vector table represent offsets from a base address.
Page 671 Interrupt Vector Addresses IRPTL & IMASK SFT3I EP0I User Software Interrupt 3 Ext. Port Buffer 0 (or Link Buffer 4) DMA SFT2I EP1I User Software Interrupt 2 Ext. Port Buffer 1 (or Link Buffer 5) DMA SFT1I EP2I User Software Interrupt 1 Ext.
Page 672 F Interrupt Vector Addresses F – 4 www.BDTIC.com/ADI...
Page 673 SHARC Glossary Term Definition core processor or processor core ADSP-21000 core DSP processor—program sequencer, instruction cache, timer, DAG1, DAG2, register file (R15-0), computation units. Does not include ADSP-2106x’s internal memory, external port, and I/O processor. An “action performed by the core processor” implies an action caused by the program executing on the ADSP-2106x.
Page 674 G SHARC Glossary bus transition cycle (BTC) a cycle in which control of the external bus is passed from one ADSP-2106x to another (in a multiprocessor system) host transition cycle (HTC) a cycle in which control of the external bus is passed from the ADSP-2106x to the host processor—during this cycle the ADSP-2106x stops driving the...
Page 675 SHARC Glossary single-word data transfers (host processor) reads and writes to the EPBx external port buffers, performed externally by the host or internally by the ADSP-2106x core; these occur when DMA is disabled in the DMACx control register link port vs. link buffer the link ports receive and transmit data on their LxDAT data pins;...
Page 676 G SHARC Glossary DMA parameter registers the address (II), modifier (IM), count (C), chain pointer (CP), etc., registers used to set up a DMA transfer transfer control block (TCB) a set of DMA parameter register values stored in memory that are downloaded by the ADSP-2106x’s DMA controller for chained DMA operations TCB chain loading...
Page 677 H DOCUMENTATION ERRATA This revision of the ADSP-2106x SHARC Processor User’s Manual con- tains corrections to errata in the previous, Second Edition, published May 1997. All of the pertinent corrections reported in the second edi- tion’s documentation errata on the Analog Devices Web site, , are reproduced below.
Page 678 Errata and Corrections In this case, the delayed branch instruction ; is executed R0=R0+R1 but the instruction is not executed. Also, the control R1=R1+R2 jumps to instead of , with the delayed branch instruction being the execution of The exception is for JUMP, which can be done for mutually-exclu- sive conditions for both (EQ, NE).
Page 679 DOCUMENTATION ERRATA Next, execute the following instruction before doing an RTS: pop PCSTK; rts(db); nop; nop; If pushing a PC stack, do a first and then an RTS. If a value is popped inside the delayed branch, whatever subroutine return address is pushed is popped back and this is restricted.
Page 680 Errata and Corrections 2. Write to a PC stack inside a call If the user writes to the PC stack inside a call, the value pushed onto the PC stack due to a call is overwritten by the value written onto the PC stack. Hence, when the user does an RTS, the user returns to the address pushed onto the PC stack and not to the address pushed while branching to the subroutine.
Page 681 DOCUMENTATION ERRATA For example: 20118 LCNTR=10; 20119 jump my(db); 2012C my: 2011A do my until LCE; 2011B my: r0=r0+r1; 2011C r2=r2+r3; 2011D r1=r1+r2; In the example, there is a loop inside a delayed branch. Because the loop executes the instructions inside the loop ten times, the address of the destination of the jump ( ) is flushed.
Page 682 Errata and Corrections Chapter: 3 Page: 24 Revision Needed: In paragraph 3.6.2 at the bottom of the page, second sentence, the seg- ment “eight memory locations” shou ld be replaced with “four memory locations.” Chapter: 3 Page: 41 Revision Needed: Add the following paragraph and note to the end of section 3.10.3 Cache Disable &...
Page 683 DOCUMENTATION ERRATA Chapter: 7 Page: 31 Revision Needed: The instruction should be replaced with IF NE JUMP (PC,-2); IF TF JUMP (PC,-2); Chapter: 8 Page: 8 Revision Needed: The last paragraph on this page is confusing. It should be changed to: Table 8.2 covers all cases including various multiprocessing systems.
Page 684 Errata and Corrections Chapter: A Page: 20 Revision Needed: There is a typographical error in the first compute/immediate modify example. Change as follows: From: IF FLAG0_IN F1=F5*F12, F11=PM(I10,40); IF FLAG0_IN F1=F5*F12, F11=PM(I10,4); Chapter: A Page: 24 Revision Needed: There is a typographical error in the first line of the immediate shift exam- ple.
Page 685 DOCUMENTATION ERRATA Chapter: E Page: 50 Revision Needed: The bit fields shown are for the SPORT Receive Control register, not the Transmit Control register. See Figure 10.2 on page 10-10 for the correct bit fields of the Transmit Control register. Chapter: E Page: 51 Revision Needed: Bit 20 of the SRCTLx register is incorrectly marked as being reserved.
Page 686 Errata and Corrections H-10 www.BDTIC.com/ADI...
Page 687 Index Index Symbols ALU saturation ..2-6, B-4, B-5, B-6, B-7, ......B-10, B-11, B-12, B-13, µ-law companding ......... 10-18 ......... B-14, B-15, B-37 ALU status flags ......... 2-7 16-bit data .......... 4-4, 5-13 ALUSAT bit (MODE1 register) ..2-6, 2-7 16-bit floating-point data AN flag ........
Page 688 Index BMS ....5-39, 5-42, 11-31, 11-35, E-24 CALL instruction ..... 3-6, 3-9, 3-15 Board-level testing ......... 11-15 Capacitive loading ......... 11-22 Boot EPROM ..........E-24 Carry flag ............. 2-9 Booting ..... 3-26, 3-28, 11-27, E-34 CB15I interrupt ......... 3-25 Booting mode ..........
Page 689 Index Context switching Delay lines ........... 1-9 1-8, 1-9, 1-11, 2-12, 2-28, 4-3 Delayed branch (DB) .... 3-9, 3-10, 3-11, Core priority access (CPA) ......7-9 ......3-12, 3-24, 11-38, 11-40, Core processor .... 1-8, 1-11, 7-16, 7-17, ......A-5, A-28, A-30, A-34 ......
Page 690 Index DMA interrupts ..3-37, 6-6, 6-22, 6-23, Effect latency ........3-5, E-2 .... 6-28, 6-47, 7-27, 8-19, 9-5, 9-17, EI (external index) register ..... 6-22, ..9-19, 9-23, 10-4, 10-7, 10-36, 10-39, ..... 6-24, 6-38, 6-41, 6-47, 6-51 ..........10-41, 11-31 ELAST ............
Page 691 Index Extra cycles ... 3-15, 4-12, 5-2, 5-3, 5-5, ......5-8, 11-38, 11-39, 11-40, ..........E-9, E-29, G-4 General-purpose register (GP) ..6-22, 6-29 EZ-ICE emulator ........11-13 Glitch rejection ........11-17 EZ-ICE software ........11-15 Global memory ........... 7-4 Graphics applications ........
Page 692 Index I0 register ........... 4-10 Interrupt priority ..3-21, 3-24, 3-25, 3-27, I15 register ........... 4-9 ......... 3-28, 3-35, E-22, F-1 I7 register ............. 4-9 Interrupt sensitivity ......... 3-31 I8 register ........... 4-10 Interrupt service routine ..3-12, 3-24, 3-26, ID Code .............
Page 693 Index Latency ....3-22, 11-44, 11-47, E-2, LSRQ interrupt ......... 3-25, 9-5 ......... E-27, E-36, E-39 LSRQ register ..........9-20 LBOOT pin ..........11-32 LCE condition ..3-7, 3-8, 3-13, 3-19, 3-20 LCNTR ... 3-5, 3-13, 3-19, 3-20, A-36, A-37 M field ....
Page 694 Index MSIZE ............E-28 MSWF bit ........... 6-37 MU flag ..........2-15, 2-16 Packing ......... 1-13, 1-15, E-49 Multichannel mode ....10-17, 10-37 Packing error status ...... E-43, E-45 Multifunction instructions ..... 1-8, 1-12, Packing mode ...... 6-11, 6-37, 8-19, ...........
Page 695 Index Program memory ..1-9, 1-10, 5-3, 11-42, RFS (receive frame sync) ... 10-20, 10-26 ......... A-40, A-41, G-3 RFSDIV ............ 10-14 Program memory data ..3-4, 5-3, 5-4, G-4 Ringing ............. 11-22 Program memory data access ..1-9, 2-27, RND32 bit (MODE1 register) ....
Page 696 Index Shifter operations ........B-54 Stack full flags ........... 3-36 Shifter overflow ..... 2-24, 3-8, E-18 Stack full interrupt ........3-12 Short float data ........... C-3 Stack overflow ... 3-18, 3-21, 3-25, 3-37 Short float data format ..2-3, B-74, B-75 Stack overflow flags .........
Page 697 Index TCLKDIV ..........10-14 User-defined status flags ......3-5 TCOUNT register ......3-33, 3-34 USTAT1 ..........3-5, E-3 TDM (time division multiplexed) ..10-1, USTAT2 ..........3-5, E-3 ..........10-2, 10-25 Termination ..... 9-26, 11-16, 11-19, ..........11-21, 11-26 Vector data types ........1-6 Termination condition ....
Page 698 Index X – 12 www.BDTIC.com/ADI...

Analog Devices ADSP-2106x SHARC User Manual

Chapter 1 Introduction

CHAPTER 2 Computation Units

Computation Units

Chapter 3 Program Sequencing

Chapter 4 Data Addressing

Chapter 5 Memory

Chapter 6 Dma

Chapter 7 Multiprocessing

Chapter 8 Host Interface

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Summary of Contents for Analog Devices ADSP-2106x SHARC