Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 746

Functional Description
The TWI controller's clock output follows these rules:
• Once the clock high (
put is driven low and the clock low (
• Once the clock low count is complete, the serial clock line is
three-stated and the clock synchronization logic enters into a delay
mode (shaded area) until the
level. At this time, the clock high count begins.
The TWI controller only issues a clock during master mode operation and
only at the time a transfer has been initiated. If arbitration for the bus is
lost, the serial clock output immediately three-states. If multiple clocks
attempt to drive the serial clock line, the TWI controller synchronizes its
clock with the other remaining clocks. This is illustrated in
TWI CONTROLLER
CLOCK
SECOND MASTER
CLOCK
TWI_CLOCK
RESULT
Figure 21-2. TWI Clock Synchronization
The TWI controller follows the transfer protocol of the Philips I
Specification version 2.1 dated January 2000. A simple complete transfer is
diagrammed in
21-8
www.BDTIC.com/ADI
) count is complete, the serial clock out-
CLKHI
HIGH
COUNT
Figure 21-3.
ADSP-214xx SHARC Processor Hardware Reference
) count begins.
CLKLOW
line is detected at a logic 1
TWI_CLOCK
LOW
COUNT
Figure 21-2.
2
C Bus