Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 90

DMA Channel Registers
Table 2-10. Chain Pointer Register (CPx)
Bit
18–0
19

For the new SPORT external memory functionality, when writing
tests which involve the
be split before writing to the chain pointer register.
Table 2-11. SPORT Chain Pointer Register (CPSPx)
Bit
18–0
19
27–20
Note that the serial ports have the ability to fetch TCBs from external
memory.
Table 2-12. External Port Chain Pointer Register (EPCPx)
Bit
18–0
19
20
2-12
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Name
IIx address
PCI
bit, the external memory address should
PCI
Name
IIx address
PCI
IIx address
Name
IIx address
PCI
CPDR
ADSP-214xx SHARC Processor Hardware Reference
Description
Next chain pointer address
Program controlled interrupt
0 = no interrupt after current TCB
1 = interrupt after current TCB
Description
Next chain pointer address (bits 18–0 of
the chain pointer)
Program controlled interrupt
0 = no interrupt after current TCB
1 = interrupt after current TCB
Next chain pointer (external address,
bits 27–19 of the chain pointer)
Description
Next chain pointer address
Program controlled interrupt
0 = no interrupt after current TCB
1 = interrupt after current TCB
DMA direction for next TCB
0 = write to internal memory
1 = read from internal memory