Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 894

Peripheral Registers
Writes to the enable and disable bit-pairs for a PWM group works as
follows.
= 0,
PWM_DISx PWM_ENx
= 0,
PWM_DISx PWM_ENx
= 1,
PWM_DISx PWM_ENx
For reads, the interpretation is as follows.
= 0,
PWM_DISx PWM_ENx
= 1,
PWM_DISx PWM_ENx
Any other read combination is not possible. Reads of the
returns the enable status on both the enable and disable bits.
15
PWM_SYNCDIS3
PWM Group 3 Disable
PWM_SYNCEN3
PWM Group 3 Enable
PWM_SYNCDIS2
PWM Group 2 Disable
PWM_SYNCEN2
PWM Group 2 Enable
PWM_SYNCDIS1
PWM Group 1 Disable
PWM_SYNCEN1
PWM Group 1 Enable
PWM_SYNCDIS0
PWM Group 0 Disable
PWM_SYNCEN0
PWM Group 0 Enable
Figure A-31. PWMGCTL Register
Table A-35. PWMGCTL Register Bit Descriptions (RW)
Bit
0, 2. 4, 6
1, 3, 5, 7
A-68
www.BDTIC.com/ADI
= 0 – No action
= 1 – Enable the PWM group
= x – Disable the PWM group
= 0 – PWM group is disabled
= 1 – PWM group is enabled
14 13 12 11 10 9 8 7
Name
PWM_ENx0
PWM_DISx
ADSP-214xx SHARC Processor Hardware Reference
6 5 4 3 2 1 0
PWM_EN0
PWM Group 0 Enable
PWM_DIS0
PWM Group 0 Disable
PWM_EN1
PWM Group 1 Enable
PWM_DIS1
PWM Group 1 Disable
PWM_EN2
PWM Group 2 Enable
PWM_DIS2
PWM Group 2 Disable
PWM_EN3
PWM Group 3 Enable
PWM_DIS3
PWM Group 3 Disable
Function
PWM Group x Enable
PWM Group x Disable
register
PWMGCTL