Read From Local Memory; Fir Accelerator; Features - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

FIR Accelerator

Read from Local Memory

1. Enable FFT module using the
2. Wait at least 4
3. Clear the
4. Set the
FFT_DBG
5. Write address to the
determine which memory to read.
6. Wait at least 20
register.
FIR Accelerator
Finite Impulse Response (FIR) filters are used in a wide array of applica-
tions, and can be used in multi-rate processing in conjunction with an
interpolator or decimator.

Features

This hardware module is capable of performing FIR filters without core
intervention. This gives programs freedom to use the core to implement
complex algorithms, effectively adding more bandwidth to the processor.
• FIR supports fixed point and IEEE floating point format
• Single rate or multi-rate window processing
• Change the rates with decimation or interpolation mode
• Up to 32 filter channels available
6-28
www.BDTIC.com/ADI
cycles.
CCLK
bit in the
FFT_DMAEN
bit in the
FFTCTL1
FFTDADDR
cycles before writing data to
CCLK
ADSP-214xx SHARC Processor Hardware Reference
register.
PMCTL1
register.
FFTCTL1
register.
register. The MSB address bits
FFTDDATA