Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 578

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S/PDIF Transmitter

off-board connections to other S/PDIF receivers. The output is also avail-

able to the S/PDIF receiver for loop-back testing through SRU.

In addition to encoding the audio data in the bi-phase format, the trans-

mitter also provides a way to easily add the channel status information to

the outgoing bi-phase stream. There are status/user registers for a frame

(192-bits/24 bytes) in the transmitter that correspond to each channel or

subframe. For more information, see

DIT_EXTSYNC_I

Figure 13-1. S/PDIF Transmitter Block Diagram

Validity bits for both channels may also be controlled by the transmitter

control register. Optionally, the user bit, validity bit, and channel status

bit are sent to the transmitter with each left/right sample. For each sub-

frame the parity bit is automatically generated and inserted into the

bi-phase encoded data. A mute control and support for double-frequency

single-channel mode are also provided. The serial data input format may

be selected as left-justified, I

www.BDTIC.com/ADI

"Transmitter Registers" on

CONTROL REGISTER

TX_BIPHASE_CLK

S, or right-justified with 16-, 18-, 20- or

ADSP-214xx SHARC Processor Hardware Reference

(BIPHASE OUT)

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