External Port Dma Bus; Sport/External Port Dma Bus - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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In the fixed priority scheme, the lower indexed peripheral has the highest

External Port DMA Bus

External port DMA channels transfer data between internal memories or

between internal and external memory over the IOD1 bus. When both

external port channels request access to the IOD1 bus in a clock cycle, the

external port bus arbiter, which is attached to the IOD1 bus, determines

which master should have access to the bus and grants the bus to that

IOP/external port channel arbitration can be set to use either a fixed or

rotating algorithm by setting or clearing the

ter as follows.

• (=10) fixed arbitration channel 0 high

• (=11) rotating arbitration (default)

Note the independency is only broken if there is an internal memory

block conflict. In this case, if both rotating bits are set, the peripheral

DMA channels always have the highest priority and the

the change in priority among the two external port DMA channels.

The data connection between the SPORT and the external port is per-

formed over the SPEP (SPORT/External Port) DMA bus. Note that it is

possible to run two independent SPORT DMA channels in parallel: the

first over the SPORT to the external port and the second from any other

SPORT to the internal memory.

ADSP-214xx SHARC Processor Hardware Reference

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I/O Processor

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