Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 318

FFT Accelerator
LOG2HDIM
FFT_RPT
FFT_CPACKIN
input/output data is packed into complex words or sent/received
data is real or imaginary.
3. Set (=1) the
imum of 4
4. Program control register
FFT_RST
= 1
FFT_EN
FFT_START
FFT_DMAEN
FFT_DEBUG
5. Configure a coefficient DMA to read N complex twiddle factors
from the coefficient buffer into the accelerator (total of 2N 32- bit
words) and wait until the DMA is complete (or chain DMA in Step
4). This step is not needed if twiddles are already in the coefficient
memory of the accelerator.
6. Configure a data DMA to read N complex data points from the
input buffer into the accelerator (total of 2N 32-bit words).
7. Configure a data DMA to write N complex data points from the
accelerator into the output buffer (total of 2N 32-bit words). There
is no need to wait until the DMA in Step 6 completes.
8. Wait until the DMA in Step 7 completes (by interrupt or polling).
The computed FFT is now in the core's internal memory and the
accelerator is in idle mode.
N <= 256, Repeat
For details on the storage format of the coefficients see
Storage" on page 6-8
6-22
www.BDTIC.com/ADI
= 0
= 0
/
FFT_CPACKOUT
bit in the
FFT_RST
cycles.
CCLK
FFTCTL1
= 0
= 1
= 1
= 0
.
ADSP-214xx SHARC Processor Hardware Reference
= 0 or 1 depending on whether
register and wait for a min-
FFTCTL1
with:
"Internal Memory