Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 754

Interrupts
Table 21-4. TWI Interrupt Overview
Interrupt Interrupt Condition
Source
DPI TWI – Master (TX completion, TX/RX
(TX/RX) buffer service, error)
– slave (initiative, completion,
overflow, error)
TWI(TX/RX) – Master (TX completion, TX/RX
buffer service, error)
– slave (initiative, completion,
overflow, error)
Interrupt Routing
The following sections describe the various possibilities for routing a TWI
interrupt to the interrupt vector table (IVT).
DPI
The TWI interrupt is combined into the digital peripheral interface (DPI)
interrupt. The
DPI_IRPTL
erated. Listing 21-1
DPI.
Listing 21-1. Enabling DPI TWI Interrupts
bit set mode1 IRPTEN;
bit set imask DPII;
ustat1 = TWI_INT;
dm(DPI_IRPTL_RE) = ustat1;
TWI
The TWI receive and transmit interrupts can also be programmed
through the peripheral interrupt control registers (
21-16
www.BDTIC.com/ADI
register determines whether an interrupt is gen-
shows an example of how to enable the TWI over the
/* enables global interrupts */
/* unmasks DPI interrupt */|
/* unmasks TWI interrupt */
ADSP-214xx SHARC Processor Hardware Reference
Interrupt Interrupt
Completion Acknowledge
Internal transfer W1C (Write one
completion to clear) TWI-
IRPTL register +
RTI instruction
Internal transfer W1C (Write one
completion to clear) TWI-
IRPTL register +
RTI instruction
) as separate inter-
PICRx
Default IVT
P14I
Need to route
TWII (PICRx)
to any PxxI