Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 500

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Data Transfers

If the SPORTs are configured as transmitters, programs should not

write to the inactive

writing to the inactive buffer, the transmit buffer status becomes

full. This causes the core to hang indefinitely since data is never

transmitted to the output shift register.

If the SPORTs are configured as receivers, programs should not

read from the inactive

reading from to the inactive buffer, the receive buffer status

becomes empty. This causes the core to hang indefinitely since new

data is never received via the input shift register.

The status bits in

the core processor even when the serial port is disabled. Disable the

serial port when writing to the receive buffer or reading from the

transmit buffer.

Data Buffer Packing

Received data words of 16 bits or less may be packed into 32-bit words,

and 32-bit words being transmitted may be unpacked into 16-bit words.

Word packing and unpacking is selected by the

control registers.

= 1 in the control register, two successive words received are

packed into a single 32-bit word, and each 32-bit word is unpacked and

transmitted as two 16-bit words. The first 16-bit (or smaller) word is

right-justified in bits 15–0 of the packed word, and the second 16-bit (or

smaller) word is right-justified in bits 31–16. This applies to both receive

(packing) and transmit (unpacking) operations. Companding can be used

with word packing or unpacking.

When serial port data packing is enabled, the transmit and receive inter-

rupts are generated for the 32-bit packed words, not for each 16-bit word.

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are updated during reads and writes from

ADSP-214xx SHARC Processor Hardware Reference

buffers. If the core keeps

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