Internal Index Register Addressing - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Internal Index Register Addressing

All addresses in the index registers are offset by a value matching the pro-
cessor's first internal normal word addressed RAM location, before the
I/O processor uses the addresses. For the ADSP-214xx processors, this off-
set value is 0x0008 0000.
The following rules for data transfers must be followed.
• DMA index addresses must always be normal word space (32-bit).
• The I/O processor can transfer short word data (16-bit or 8-bit)
using the packing capability of the peripherals (serial port or SPI).
The data are packed in the peripheral's shift register to form 32-bit
words for the internal transfers over the IOD0 and IOD1 buses.
After transferring each data word to or from internal memory, the I/O
processor adds the modify value to the index register to generate the
address for the next DMA transfer and writes the modified index value to
the index register. The modify value in the modify register is a signed inte-
ger, which allows both increment and decrement modifies. The modify
value can have any positive or negative integer value. Note that:
• If the I/O processor modifies the internal index register past the
maximum 19-bit value to indicate an address out of internal mem-
ory, the index wraps around to zero. With the offset for the
SHARC processor, the wraparound address is 0x80000.
• If a DMA channel is disabled, the I/O processor does not service
requests for that channel, whether or not the channel has data to
transfer.

If a program loads the count register with zero, the I/O processor
does not disable DMA transfers on that channel. The I/O proces-
sor interprets the zero as a request for 2
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
I/O Processor
16
transfers. This count
2-27