Analog Devices ADSP-21367 Manual

Sharc processors

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SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—2M bits of on-chip SRAM and 6M bits of

on-chip mask programmable ROM

Code compatible with all other members of the SHARC family

CORE PROCESSOR

DAG2

DAG1

PM ADDRESS BUS

DM ADDRESS BUS

PROCESSING

ELEMENT

(PEY)

(PEX)

GPIO FLAGS/

IRQ/TIMEXP

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

INSTRUCTION

CACHE

TIMER

32 48-BIT

PROGRAM

SEQUENCER

PM DATA BUS

DM DATA BUS

PX REGISTER

PRECISION CLOCK

GENERATORS (4)

SRC (8 CHANNELS)

SPDIF (Rx/Tx)

DIGITAL APPLICATIONS INTERFACE

Figure 1. Functional Block Diagram

ADSP-21367/ADSP-21368/ADSP-21369

The ADSP-21367/ADSP-21368/ADSP-21369 are available

with a 400 MHz core instruction rate with unique audiocen-

tric peripherals such as the digital applications interface,

S/PDIF transceiver, serial ports, 8-channel asynchronous

sample rate converter, precision clock generators, and

more. For complete ordering information, see

Guide on Page

4 BLOCKS OF

ON-CHIP MEMORY

2M BIT RAM

6M BIT ROM

ADDR

DATA

IOA(19)

IOD(32)

IOP REGISTER (MEMORY MAPPED)

CONTROL, STATUS, AND DATA BUFFERS

SERIAL PORTS (8)

INPUT DATA PORT/

PDAP

DAI PINS

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

SHARC Processors

55.

JTAG TEST & EMULATION

FLAGS0-15

4 PWMs

EXTERNAL PORT

SDRAM

CONTROLLER

ASYNCHRONOUS

MEMORY INTERFACE

SHARED MEMORY

INTERFACE

DMA

CONTROLLER

34 CHANNELS

MEMORY DMA (2)

SPI PORT (2)

2-WIRE

INTERFACE

DPI PINS

DIGITAL PERIPHERAL INTERFACE

I/O PROCESSOR

www.analog.com

Ordering

DATA

CONTROL

ADDRESS

MEMORY-TO-

UART (2)

TIMERS (3)

Table of Contents

Summary of Contents for Analog Devices ADSP-21367

Page 1 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use.
Page 2: Key Features—Processor Core
ADSP-21367/ADSP-21368/ADSP-21369 KEY FEATURES—PROCESSOR CORE Digital peripheral interface (DPI) includes three timers, two UARTs, two SPI ports, and a 2-wire interface port At 400 MHz (2.5 ns) core instruction rate, the processors per- Outputs of PCGs C and D can be driven on to DPI pins form 2.4 GFLOPS/800 MMACS...
Page 3: Table Of Contents
ADSP-21367/ADSP-21368/ADSP-21369 TABLE OF CONTENTS REVISION HISTORY Summary ............... 1 11/08—Rev. C to Rev. D Key Features—Processor Core ......... 2 Corrected all outstanding document errata. Input/Output Features ........... 2 Changed digital audio interface to digital applications interface throughout this document. This change is a naming convention Dedicated Audio Components .........
Page 4: General Description
• On-chip SRAM (2M bit) sors are members of the SIMD SHARC family of DSPs that • On-chip mask-programmable ROM (6M bit) feature Analog Devices’ Super Harvard Architecture. These pro- • JTAG test access port cessors are source code-compatible with the ADSP-2126x and...
Page 5: Memory Architecture
The Circular Buffer Support 32-bit wide bus can be used to interface to synchronous and/or The ADSP-21367/ADSP-21368/ADSP-21369 have two data asynchronous memory devices through the use of its separate address generators (DAGs). The DAGs are used for indirect internal memory controllers.
Page 6 0x000E 2000–0x000F FFFF 0x001C 4000–0x001F FFFF The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details. A set of programmable timing parameters is available to config- Table 4. External Memory for SDRAM Addresses ure the SDRAM banks to support slower memory devices.
Page 7: I/O Processor Features
• Two universal asynchronous receiver/transmitters that provide an inexpensive interface to a wide variety of digital (UARTs) and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial • A 2-wire interface (TWI, I C-compatible) ports are made up of two data lines, a clock, and frame sync.
Page 8 SPI-compatible devices, either monly used by audio codecs, ADCs, and DACs such as the acting as a master or slave device. The ADSP-21367/ Analog Devices AD183x family), with two data pins, allowing ADSP-21368/ADSP-21369 SPI-compatible peripheral imple-...
Page 9: System Design
3-phase PWM inverters. baud detection is supported. ROM-Based Security Timers The ADSP-21367/ADSP-21368/ADSP-21369 have a ROM secu- The ADSP-21367/ADSP-21368/ADSP-21369 have a total of rity feature that provides hardware support for securing user four timers: a core timer that can generate periodic software...
Page 10: Development Tools
• Fill, dump, and graphically plot the contents of memory Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21367/ • Perform source level debugging ADSP-21368/ADSP-21369 processors to monitor and control •...
Page 11: Additional Information
Designing an Emulator-Compatible DSP Board (Target) 2136x/ADSP-2137x SHARC Processor Programming Reference. The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP.
Page 12: Pin Function Descriptions
PIN FUNCTION DESCRIPTIONS The following symbols appear in the Type column of Table The ADSP-21367/ADSP-21368/ADSP-21369 SHARC proces- A = asynchronous, G = ground, I = input, O = output, sors use extensive pin multiplexing to achieve a lower pin count.
Page 13 O/T (pu) Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/ ADSP-21369 Analog Devices DSP Tools product line of JTAG emulator target board connectors only. Rev. D | Page 13 of 56 | November 2008...
Page 14 This signal is a system configuration selection which must be set to the same value on every processor in the system. The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID = 00x 2–0...
Page 15: Data Modes
ADSP-21367/ADSP-21368/ADSP-21369 DATA MODES The upper 32 data pins of the external memory interface are muxed (using bits in the SYSCTL register) to support the exter- nal memory interface data (input/output), the PDAP (input only), the FLAGS (input/output), and the PWM channels (out- put).
Page 16: Specifications
ADSP-21367/ADSP-21368/ADSP-21369 SPECIFICATIONS OPERATING CONDITIONS 400 MHz 350 MHz 333 MHz 266 MHz Parameter Description Unit Internal (Core) Supply Voltage 1.25 1.35 1.235 1.365 1.14 1.26 1.14 1.26 DDINT Analog (PLL) Supply Voltage 1.25 1.35 1.235 1.365 1.14 1.26 1.14 1.26 External (I/O) Supply Voltage 3.13...
Page 17: Package Information
The information presented in Figure 3 provides details about Parameter Rating the package branding for the ADSP-21367/ADSP-21368/ Internal (Core) Supply Voltage (V –0.3 V to +1.5 V DDINT ADSP-21369 processors. For a complete listing of product avail- Analog (PLL) Supply Voltage (A –0.3 V to +1.5 V...
Page 18 ADSP-21367/ADSP-21368/ADSP-21369 Table 12. Clock Periods reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Timing Figure 39 on Page 46 under Test Conditions for voltage refer- Requirements Description ence levels.
Page 19 ADSP-21367/ADSP-21368/ADSP-21369 Power-Up Sequencing The timing requirements for processor start-up are given in driven low before power up is complete. This leakage current Table 13. Note that during power-up, a leakage current of results from the weak internal pull-up resistor on this pin being approximately 200μA may be observed on the RESET pin if it is...
Page 20 ADSP-21367/ADSP-21368/ADSP-21369 Clock Input Table 14. Clock Input 400 MHz 350 MHz 333 MHz 266 MHz Parameter Unit Timing Requirements CLKIN Period 17.14 22.5 CLKIN Width Low 11.25 CLKIN Width High 11.25 CLKIN Rise/Fall (0.4 V to 2.0 V) CKRF CCLK Period 2.85...
Page 21 ADSP-21367/ADSP-21368/ADSP-21369 Reset Table 15. Reset Parameter Unit Timing Requirements RESET Pulse Width Low WRST RESET Setup Before CLKIN Low SRST Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable and CLKIN (not including start-up time of external clock oscillator).
Page 22 ADSP-21367/ADSP-21368/ADSP-21369 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER). Table 17. Core Timer Parameter Unit Switching Characteristic CTIMER Pulse Width 4 × t – 1 WCTIM PCLK FLAG3 WCTIM (CTIMER) Figure 10.
Page 23 ADSP-21367/ADSP-21368/ADSP-21369 Timer WDTH_CAP Timing The following specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the specification provided in Table 19 valid at the DPI_P14–1 pins.
Page 24 ADSP-21367/ADSP-21368/ADSP-21369 Precision Clock Generator (Direct Pin Routing) inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing param- This timing is only valid when the SRU is configured such that...
Page 25 ADSP-21367/ADSP-21368/ADSP-21369 Flags The timing specifications provided below apply to the FLAG3–0 and DPI_P14–1 pins, and the serial peripheral interface (SPI). Table 5 on Page 12 for more information on flag use. Table 22. Flags Parameter Unit Timing Requirement FLAG3–0 IN Pulse Width 2 ×...
Page 26 ADSP-21367/ADSP-21368/ADSP-21369 SDRAM Interface Timing (166 MHz SDCLK) = 2.5 × t The 166 MHz access speed is for a single processor. When mul- The processor needs to be programmed in t SDCLK CCLK tiple ADSP-21368 processors are connected in a shared memory mode when operated at 350 MHz.
Page 27 ADSP-21367/ADSP-21368/ADSP-21369 SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Table 24. SDRAM Interface Enable/Disable Timing Parameter Unit Switching Characteristics Command Disable After CLKIN Rise 2 × t DSDC PCLK Command Enable After CLKIN Rise ENSDC SDCLK Disable After CLKIN Rise DSDCC...
Page 28 ADSP-21367/ADSP-21368/ADSP-21369 Memory Read Use these specifications for asynchronous interfacing to memo- ries. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
Page 29 ADSP-21367/ADSP-21368/ADSP-21369 Memory Write access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access Use these specifications for asynchronous interfacing to memo- mode. ries. These specifications apply when the processors are the bus masters, accessing external memory space in asynchronous Table 26.
Page 30 ADSP-21367/ADSP-21368/ADSP-21369 Asynchronous Memory Interface (AMI) Enable/Disable Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 27. AMI Enable/Disable Parameter Unit Switching Characteristics Address/Control Enable After Clock Rise ENAMIAC Data Enable After Clock Rise ENAMID SDCLK Address/Control Disable After Clock Rise...
Page 31 ADSP-21367/ADSP-21368/ADSP-21369 Shared Memory Bus Request Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 28. Multiprocessor Bus Request Parameter Unit Timing Requirements BRx, Setup Before CLKIN High SBRI BRx, Hold After CLKIN High HBRI Switching Characteristics BRx Delay After CLKIN High...
Page 32 ADSP-21367/ADSP-21368/ADSP-21369 Serial Ports To determine whether communication is possible between two Serial port signals SCLK, frame sync (FS), data channel A, data devices at clock speed n, the following specifications must be channel B are routed to the DAI_P20–1 pins using the SRU.
Page 33 ADSP-21367/ADSP-21368/ADSP-21369 Table 30. Serial Ports—Internal Clock Parameter Unit Timing Requirements FS Setup Before SCLK SFSI (Externally Generated FS in Either Transmit or Receive Mode) FS Hold After SCLK HFSI (Externally Generated FS in Either Transmit or Receive Mode) Receive Data Setup Before SCLK...
Page 34 ADSP-21367/ADSP-21368/ADSP-21369 EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE DAI_P20 (SCLK) SFSE/I HFSE/I DAI_P20 (FS) DDTE/I DDTENFS HDTE/I DAI_P20 (DATA CHANNEL A/B) 1ST BIT 2ND BIT DDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE DAI_P20...
Page 35 ADSP-21367/ADSP-21368/ADSP-21369 DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE SCLKIW SCLKW DAI_P20 DAI_P20 (SCLK) (SCLK) DFSIR DFSE HFSI HFSE SFSI HOFSIR HOFSE SFSE DAI_P20 DAI_P20 (FS) (FS) HDRE SDRI HDRI SDRE DAI_P20 DAI_P20 (DATA CHANNEL A/B) (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
Page 36 ADSP-21367/ADSP-21368/ADSP-21369 Input Data Port The timing requirements for the IDP are given in Table 33. IDP signals SCLK, frame sync (FS), and SDATA are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DAI_P20–1 pins.
Page 37 ADSP-21367/ADSP-21368/ADSP-21369 Parallel Data Acquisition Port (PDAP) Reference. Note that the most significant 16 bits of external PDAP data can be provided through the DATA31–16 pins. The The timing requirements for the PDAP are provided in remaining four bits can only be sourced through DAI_P4–1.
Page 38: Verter—Serial Input Port
ADSP-21367/ADSP-21368/ADSP-21369 Pulse-Width Modulation Generators Table 35. PWM Timing Parameter Unit Switching Characteristics PWM Output Pulse Width – 2 – 2) × t – 2 PWMW PCLK PCLK PWM Output Period 2 × t – 1.5 – 1) × t – 1.5...
Page 39 ADSP-21367/ADSP-21368/ADSP-21369 Sample Rate Converter—Serial Output Port and delay specification with regard to SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the For the serial output port, the frame-sync is an input and it drive edge.
Page 40 ADSP-21367/ADSP-21368/ADSP-21369 S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms Figure 29 shows the right-justified mode. LRCLK is high for the Serial data input to the S/PDIF transmitter can be formatted as left channel and low for the right channel. Data is valid on the...
Page 41 ADSP-21367/ADSP-21368/ADSP-21369 S/PDIF Transmitter Input Data Timing The timing requirements for the input port are given in Table 38. Input signals SCLK, frame sync (FS), and SDATA are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins.
Page 42 ADSP-21367/ADSP-21368/ADSP-21369 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 40. S/PDIF Receiver Internal Digital PLL Mode Timing...
Page 43 ADSP-21367/ADSP-21368/ADSP-21369 SPI Interface—Master The processors contain two SPI ports. The primary has dedi- cated pins and the secondary is available through the DPI. The timing provided in Table 41 Table 42 on Page 44 applies to both. Table 41. SPI Interface Protocol—Master Switching and Timing Specifications...
Page 44 ADSP-21367/ADSP-21368/ADSP-21369 SPI Interface—Slave Table 42. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Unit Timing Requirements Serial Clock Cycle 4 × t – 2 SPICLKS PCLK Serial Clock High Period 2 × t – 2 SPICHS PCLK Serial Clock Low Period 2 ×...
Page 45 ADSP-21367/ADSP-21368/ADSP-21369 JTAG Test Access Port and Emulation Table 43. JTAG Test Access Port and Emulation Parameter Unit Timing Requirements TCK Period TDI, TMS Setup Before TCK High STAP TDI, TMS Hold After TCK High HTAP System Inputs Setup Before TCK High...
Page 46: Output Drive Currents
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Page 47 ADSP-21367/ADSP-21368/ADSP-21369 RISE RISE FALL y = 0.049x + 1.5105 y = 0.0372x + 0.228 FALL y = 0.0482x + 1.4604 y = 0.0277x + 0.369 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) Figure 41. Typical Output Rise/Fall Time Figure 43. SDCLK Typical Output Rise/Fall Time...
Page 48: Thermal Characteristics
Ψ °C/W Airflow = 2 m/s THERMAL CHARACTERISTICS Table 45. Thermal Characteristics for 208-Lead LQFP EPAD The ADSP-21367/ADSP-21368/ADSP-21369 processors are (With Exposed Pad Soldered to PCB) rated for performance over the temperature range specified in Operating Conditions on Page Parameter...
Page 49: 256-Ball Bga_Ed Pinout
ADSP-21367/ADSP-21368/ADSP-21369 256-BALL BGA_ED PINOUT Table 46. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal DAI5 DAI9 DAI10 SDCLK1 DAI7 DAI6 TRST CLK_CFG0 DDEXT DDEXT CLK_CFG1 BOOT_CFG0 BOOT_CFG1 DDEXT...
Page 50 ADSP-21367/ADSP-21368/ADSP-21369 Table 46. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) (Continued) Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal DDINT DDINT DDEXT DDINT DDINT GND/ID1 GND/ID0 DATA15 DATA12 DATA17 DATA16 DATA14 DATA13 SDA10 SDWE SDCKE...
Page 51 ADSP-21367/ADSP-21368/ADSP-21369 Figure 47 shows the bottom view of the BGA_ED ball configu- ration. Figure 48 shows the top view of the BGA_ED ball configuration. BOTTOM VIEW VIEW DDINT DDEXT DDINT DDEXT I/O SIGNALS NO CONNECT I/O SIGNALS NO CONNECT Figure 47. 256-Ball BGA_ED Ball Configuration (Bottom View) Figure 48.
Page 52: 208-Lead Lqfp_Ep Pinout
ADSP-21367/ADSP-21368/ADSP-21369 208-LEAD LQFP_EP PINOUT Table 47. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal CLK_CFG0 DDINT DDINT DDEXT DDINT DATA28 DATA4 BOOT_CFG0 DATA27 DATA5 CLK_CFG1...
Page 53: Package Dimensions
ADSP-21367/ADSP-21368/ADSP-21369 PACKAGE DIMENSIONS The ADSP-21367/ADSP-21368/ADSP-21369 processors are available in 256-ball RoHS compliant and leaded BGA_ED, and 208-lead RoHS compliant LQFP_EP packages. 30.20 30.00 SQ 25.50 29.80 28.10 1.60 MAX 8.712 28.00 SQ 0.75 27.90 0.60 0.45 1.00 REF PIN 1...
Page 54: Surface-Mount Design
ADSP-21367/ADSP-21368/ADSP-21369 A1 CORNER INDEX AREA 20 18 15 13 A1 BALL INDICATOR BOTTOM VIEW 27.00 TOP VIEW BSC SQ 24.13 DETAIL A REF SQ 1.00 1.27 0.80 1.70 MAX DETAIL A 0.60 0.70 0.60 0.10 0.50 0.20 COPLANARITY SEATING PLANE 0.90...
Page 55: Automotive Products
ADSP-21367/ADSP-21368/ADSP-21369 AUTOMOTIVE PRODUCTS An ADSP-21369 model is available for automotive applications The automotive grade product shown in Table 49 is available with controlled manufacturing. Note that this special model for use in automotive applications. Contact your local ADI may have specifications that differ from the general release account representative or authorized ADI product distributor models.
Page 56: Rev. D | Page 3 Of 56 | November
ADSP-21367/ADSP-21368/ADSP-21369 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05267-0-11/08(D) Rev. D | Page 56 of 56 | November 2008...

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