Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 211

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DDR2 access occurs and the DDR2 exits from self-refresh mode.

The minimum time between a subsequent self-refresh entry and

exit command is the t

during any external port DMA, the DDR2 controller grants the

request with the t

Single-Ended Data Strobe

DDR2 data strobe mode is specified for either single ended or differential

mode, depending on the setting of the EMR register enable DDR2_DQS

mode bit. The timing advantages of differential mode are realized in sys-

The method by which the DDR2 pin timing is measured is mode depen-

dent. In single ended mode, timing relationships are measured relative to

the rising or falling edges of

mode, these timing relationships are measured relative to the crosspoint of

S and its complement,

methods is guaranteed by design and characterization. When differential

data strobe mode is disabled via the

, must be tied externally to VSS through a 20 Ω to 10 kΩ resistor

to insure proper operation.

On Die Termination (ODT)

The DDR2 controller contains a separate pin (

on-die termination. By default this pin is deasserted. If during power-up,

pin is asserted after the power-up sequence has finished.

The level can be changed by forcing another power-up sequence which

disables Rtt resistance in the

deasserted. Note that the

data access directions (read or write).

ADSP-214xx SHARC Processor Hardware Reference

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cycle. If a self-refresh request is issued

cycle and continues DMA operation

crossing at VREF. In differential

. This distinction in timing

field. After completion, the

pin control is independent on the DDR2

External Port

) that controls

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