Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 458

Programming Model
SOURCE FROM
DVD PLAYER
S/PDIF serial
protocal containing
multichannel audio
sampled at 48 KHz
and compressed in AC3
BRING DATA INTO SHARC CORE
Three synchronized (but separate)
stereo streams sampled at 44.1 KHz
are brought back to
the core for
IDP
reverb,
CHANNEL_1
EQ and
CHANNEL_2
other effects
CHANNEL_3
STEREO MIX
SPORT1
If the system has only
2 speakers, this
stereo DAC can be used
instead of the 5.1
The SHARC runs a
spaitial effects
algorithm for virtual
rear speakers.
PIN_9 PIN_8 PIN_7
DATA
FS
CLK
External 8-bit macro for scanning
for button presses, knobs, etc.
Figure 9-16. DAI Example
9-44
www.BDTIC.com/ADI
S/PDIF
STREAM
PIN_1
TRANSLATE PROTOCOL
CONNECT TO S/PDIF RX
On-chip DPLL used to
recover clock and frame sync
SAMPLE RATE CONVERSION
Convert using chaining mode
multichannel channels are extracted
and the rate conversion ratio is
phase locked channel to channel.
2
I S DATA (3 STEREO PAIRS)
SHARC
CORE
SPORT2
SPORT3
SERIAL
DATA
FRAME
SERIAL
SYNC
DATA
PIN_9 PIN_8
MIX_FS MIX_DAT FL_FR_DAT
ADSP-214xx SHARC Processor Hardware Reference
CLOCK
FRAME SYNC
S/PDIF
SERIAL DATA
RECEIVER
2
I S DATA INTO SHARC CORE
5.1 channel surround
sound sampled at 48 KHz
SRC2 SRC1 SRC0
44.1 KHz
SAMPLE CLOCK OUTPUT
MULTICHANNEL RATE
The output of the PCG is
routed to a pin and the
output sample rate clock
is also routed to the same pin.
SPORT4 SPORT5
SERIAL
SERIAL
DATA
DATA
PIN_7 PIN_6 PIN_5
CTR_LFE_DAT RL_RR_DAT
IDP
SHARC
CHANNEL0
CORE
AC3 (Dolby Digital)
decompression algorithm
is executed in software
SPORT0
44.1 KHz
PCG
Low Jitter
DAC Clock
(44.1 KHz)
for both SRCs
FRAME and external
SYNC
DACs
PIN_4 PIN_3 PIN_2
FS SCLK MCLK