Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 576

Register Overview
Table 13-5. S/PDIF DAI/SRU Receiver Signal Connections (Cont'd)
Internal Node
Outputs
DIR_CLK_O
DIR_TDMCLK_O
DIR_FS_O
DIR_DAT_O
DIR_LRCLK_FB_O
DIR_LRCLK_REF_O
Register Overview
This section provides brief descriptions of the major registers. For com-
plete information see
page A-199.
Transmit Control Register (DITCTL). The
trol parameters for the S/PDIF transmitter. The control parameters
include transmitter enable, mute information, over sampling clock divi-
sion ratio, SCDF mode select and enable, serial data input format select
and validity and channel status buffer selects.
Transmit Channel Status Registers (DITCHANAx/Bx). These registers
provide status bit information for transmitter subframe A and B in stand-
alone mode.
Transmit User Bit Registers (DITUSRBITAx/Bx). These registers pro-
vide user bit information for transmitter subframe A and B in standalone
mode.
Receive Control Register (DIRCTL). The
trol parameters for the S/PDIF receiver. The control parameters include
mute information, error controls, SCDF mode select and enable, and
S/PDIF PLL disable.
13-6
www.BDTIC.com/ADI
DAI Group
Group A, D
Group C, D
Group B, D
Group D
"Sony/Philips Digital Interface Registers" on
ADSP-214xx SHARC Processor Hardware Reference
SRU Register
register contains con-
DITCTL
register contains con-
DIRCTL