Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 670

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Operating Modes

The count registers are reset to 0x0000 0001 again, and the timer contin-

ues counting until it is either disabled or the count value reaches

0xFFFF FFFF.

In this mode, programs can measure both the pulse width and the pulse

period of a waveform. To control the definition of the leading edge and

trailing edge of the

set or cleared. If the

falling edge, the count register is captured to the

ing edge, and the period register is captured on the next falling edge.

rupt is generated when the pulse width or pulse period is captured. If the

bit is set, the interrupt latch bit (

period value is captured. If the

set when the pulse width value is captured.

bit is cleared, the first period value has not yet been mea-

sured when the first interrupt is generated. Therefore, the period value is

not valid. If the interrupt service routine reads the period value anyway,

the timer returns a period value of zero. When the period expires, the

period value is loaded in the

A timer interrupt (if enabled) is also generated if the count register reaches

a value of 0xFFFF FFFF. At that point, the timer is disabled automati-

cally, and the

clear them. The WDTH_CAP timing is shown in

The first width value captured in WDTH_CAP mode is erroneous due to

synchronizer latency. To avoid this error, programs must issue two

instructions between setting WDTH_CAP mode and setting

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bit is cleared, the measurement is initiated by a

status bit is set, indicating a count overflow. The

bits are sticky bits, and programs must explicitly

ADSP-214xx SHARC Processor Hardware Reference

) gets set when the pulse

bit is cleared, the

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