Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 795

Table 23-6. SPIDMAC Master/Slave Boot Settings (0x7) (Cont'd)
Bit Setting
FIFOFLSH Cleared (= 0)
INTERR Cleared (= 0)
Table 23-7. SPICTL Master Boot Settings (0x5D06)
Bit Setting
SPIEN Set (= 1)
SPIMS Set (= 1)
MSBF Cleared (= 0)
WL 10
DMISO Cleared (= 0)
SENDZ Set (= 1)
SPIRCV Set (= 1)
CLKPL Set (= 1)
CPHASE Set (= 1)
The SPI DMA channel is used when downloading the boot kernel infor-
mation to the processor. At reset, the DMA parameter registers are
initialized to the values listed in
Table 23-8. Parameter Initialization Values for SPI Master Boot
Parameter Register
SPIBAUD
SPIFLG
IISPI
IMSPI
CSPI
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Comment
FIFO flush
SPI DMA error interrupts
Comment
SPI enabled
Master device
LSB first
32-bit SPI receive shift register word length
MISO enabled
Send zeros
Receive DMA enabled
Active low SPI clock
Toggle SPICLK at the beginning of the first bit
Table
Initialization Value
0x64
0xFE01
IVT_START_ADDR
0x1
0x180
System Design
23-8.
Comment
SPICLK = PCLK/100
SPI_FLG0_O used as slave-select
Start of block 0
32-bit data transfers
×
384 32-bit transfers
23-13