Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 911

FIR DMA Status Register (FIRDMASTAT)
The information provided by this register, shown in
described in Table
data preload DMA, processing in progress, window complete, all channels
complete.
31 30
15
CURITER (13–12)
Current MAC Iteration
CURCHNL (11–7)
Current Channel
FIR_DMAACDONE
All Channels Done
FIR_DMAWDONE
Processing of Current Channel Done
FIR_DMAWRBK
Write Back Updated Index Pointers
Figure A-38. FIRDMASTAT Register
Table A-50. FIRDMASTAT Register Bit Descriptions (RO)
Bits Name
0 FIR_DMACPLD
1 FIR_DMACLD
2 FIR_DMADLD
3 FIR_DMAPPGS
4 FIR_DMAWRBK
5 (ROC) FIR_DMAWDONE
6 (ROC) FIR_DMAACDONE All Channels Done. (Sticky – Cleared on register read)
ADSP-214xx SHARC Processor Hardware Reference
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A-50, are, chain pointer loading, coefficient DMA,
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Description
Chain Pointer Loading Status. High indicates state machine
in chain pointer load state.
Coefficient Loading.
Data Preload.
MAC Processing in Progress.
Writing Back the Updated Index Registers.
Processing of Current Channel Done. (Sticky – Cleared on
register read).
Registers Reference
Figure A-38
21 20 19 18 17 16
6 5 4 3 2 1 0
FIR_DMACPLD
Chain Pointer Load Status
FIR_DMACLD
Coefficient Loading
FIR_DMADLD
Data Preload
FIR_DMAPPGS
MAC Processing in
Process
and
A-85