Dai Interrupt Priorities; Dpi Interrupt Channels; Dpi Interrupt Priorities - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Interrupts

DAI Interrupt Priorities

As described above, the DAI interrupt controller registers provide 32 inde-
pendently-configurable interrupts labeled
Just as the core has its own interrupt latch registers (
the DAI has its own latch registers (
a DAI interrupt is configured to be high priority, it is latched in the
register. When any bit in the
DAI_IMASK_H
(= 1), bit 11 in the
interrupt with high priority. When a DAI interrupt is configured to be
low priority, it is latched in the
bit in the
DAI_IMASK_L
also set and the core services that interrupt with low priority.

By default interrupts are mapped onto low priority interrupt.

DPI Interrupt Channels

The DPI can handle up to 12 interrupts as shown below.
• 1 TWI FIFO status
• 2 UART DMA channels
• 9 miscellaneous interrupts

DPI Interrupt Priorities

Just as the core has its own interrupt latch registers (
the DPI has its own latch registers (
configured, it is latched in the
register is set (= 1), bit 11 (
DPI_IMASK
and the core services that interrupt.

The DPI interrupt controller has no priority option.
9-34
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DAI_IMASK_L
register is also set and the core services that
IRPTL
DAI_IMASK_L
register is set (= 1), bit 6 in the
DPI_IMASK
DPI_IMASK
DPII
ADSP-214xx SHARC Processor Hardware Reference
.
DAI_INT31–0
and
IRPTL
and
DAI_IMASK_H
register is set
DAI_IMASK_H
register. Similarly, when any
LIRPTL
and
IRPTL
). When a DPI interrupt is
register. When any bit in the
) in the register is also set
IRPTL
),
LIRPTL
). When
register is
),
LIRPTL