Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 674

Interrupts
source without reference to the timer's interrupt signal. The
ter contains an interrupt latch bit (
indicator bit (
TIMxOVF
These sticky bits are set by the timer hardware and may be watched by
software. They need to be cleared in the
itly. To clear, write a one to the corresponding bit in the
shown in Listing
Listing 16-1. Clearing Sticky Bits
TMR0_ISR:
ustat2=TIM0IRQ;
dm(TM0STAT)=ustat2;
r10=dm(TM0CTL);
instructions;
instructions;
RTI;

Interrupt and overflow bits may be cleared simultaneously with
timer enable or disable.
To enable a timer's interrupt, set the
( ) register and unmask the timer's interrupt by setting the corre-
TMxCTL
sponding bit of the
does not set its interrupt latch (
without generating a timer interrupt, programs can set the
leaving the timer's interrupt masked.
With interrupts enabled, ensure that the interrupt service routine (ISR)
clears the
TIMxIRQ
rupt is not serviced erroneously. In external clock (
latch should be reset at the very beginning of the interrupt routine so as
not to miss any timer event.
16-18
www.BDTIC.com/ADI
TIMxIRQ
) for each timer.
16-1.
/* W1C the Timer0 bit */
/* dummy read for write latency */
register. With the
IMASK
TIMxIRQ
latch before the
RTI
ADSP-214xx SHARC Processor Hardware Reference
) and an overflow/error
register by software explic-
TMSTAT
bit in the timer's configuration
IRQEN
bit cleared, the timer
IRQEN
) bits. To poll the
instruction to assure that the inter-
EXT_CLK
regis-
TMSTAT
register as
TMSTAT
bits
TIMxIRQ
bit while
IRQEN
) mode, the