Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 785

SPI DMA Control Register (SPIDMAC). Configures the SPI as receive
DMA which generates an interrupt during boot.
SPI Slave Select Control Register (SPIFLGx). Controls the slave select
configuration for SPI as master during SPI boot.
SPI Baudrate Register (SPIBAUD). Controls the
master mode during boot.
Processor Reset
After power-up, a
good state. Table 23-1
( pin deasserted) or a software reset (setting bit 0 in the
RESET
ter) and gives an overview of the different reset methods.
Hardware Reset
All members of the SHARC processor family support the hardware reset
controlled with the
and asserting it resets the PLL. In the time it takes the PLL to acquire lock
(set to 4096
CLKIN
peripherals are held in reset. Upon completion of the 4096
the chip is brought out of reset. This is indicated on the
the valid boot modes.
page 23-7.
Table 23-1. Reset Function Overview
Reset Function
Pin
RESETOUT
Pulse
RESETOUT
PLL
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
is required to place the processor into a known
RESET
shows the differences between a hardware reset
pin. The deassertion of this pin enables the PLL
RESET
cycles), the processor, internal memory, and the
For more information, see "Processor Booting" on
Hardware Reset
Output
4096 CLKIN cycles
asserted
Yes
System Design
SPICLK
Software Reset Running Reset
Output
2 PCLK cycles asserted N/A
No
frequency for
regis-
SYSCTL
cycles,
CLKIN
pin for
RESETOUT
Input
No
23-3