Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 895

Table A-35. PWMGCTL Register Bit Descriptions (RW) (Cont'd)
Bit
8, 10, 12, 14
9, 11, 13, 15
Global Status Register (PWMGSTAT)
This register provides the status of each PWM group
status bits are set depending on the
to clear the status bits.
Table A-36. PWMGSTAT Register Bit Descriptions (W1C)
Bit
0
1
2
3
15–4
Control Register (PWMCTLx)
These registers, described in
modes of each PWM block. They also allow programs to disable interrupts
from individual groups.
15
PWM_IRQEN
Interrupt Enable
PWM_UPDATE
Update Mode
Figure A-32. PWMCTLx Register
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Name
PWM_SYNCENx
PWM_SYNCDISx
Name Function
PWM_STAT0 PWM Group 0 Period Completion Status
PWM_STAT1 PWM Group 1 Period Completion Status
PWM_STAT2 PWM Group 2 Period Completion Status
PWM_STAT3 PWM Group 3 Period Completion Status
Reserved
Table
14 13 12 11 10 9 8
Registers Reference
Function
PWM Group x Enable
PWM Group xDisable
(Table
bit. The ISR needs to write one
IRQEN
A-37, are used to set the operating
7 6 5 4 3 2 1 0
A-36). The
PWM_ALIGN
Align Mode
PWM_PAIR
Pair Mode
A-69