Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 917

IIR MAC Status Register (IIRMACSTAT)
The
IIRMACSTAT
Table A-54, provides the status of MAC operations.
15
IIR_AINV
IIR_ARI
IIR_ARZ
Figure A-42. IIRMACSTAT Register
Table A-54. IIRMACSTAT Register Bit Descriptions (RO)
Bits Name
0 IIR_MRZ
1 IIR_MRI
2 IIR_MINV
3 IIR_ARZ
4 IIR_ARI
5 IIR_AINV
31–6 Reserved
IIR DMA Status Register (IIRDMASTAT)
The IIR DMA registers are described in
The
IIRDMASTAT
Table A-55, provides the status of DMA operations. All the bits in this
register are read only.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register, shown in Figure A-42
14 13 12 11 10 9 8 7
Description
Multiplier Result Zero. Set if multiplier results is zero.
Multiplier Result Infinity. Set if multiplier results is infinity.
Multiply Invalid. Set if multiply operation is invalid.
Adder Result Zero. Set if adder results is zero.
Adder Result Infinity. Set if adder results is infinity.
Addition Invalid. Set if addition is invalid.
register, shown in Figure A-43
Registers Reference
and described in
6 5 4 3 2 1 0
IIR_MRZ
IIR_MRI
IIR_MINV
"Data Transfer" on page
and described in
6-15.
A-91