Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 973

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Data Routing Register (SRU_DAT_SHREG)

The shift register's

logic 1, SPORT0–7 data outputs,

options for the

Figure A-82. SR_DAT_SHREG Register (RW)

Table A-82. Group G Sources – Shift Register Data Routing

Selection Code

ADSP-214xx SHARC Processor Hardware Reference

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input signal can come from either logic 0 ,

shows the list of sources and programmable

input signal.

Source Signal

Registers Reference

, or DAI pin buffers 1–8.

SR_SDI_I (4–0)

Serial Data Input Enable

Description (Output Source Selection)

Logic Leve Low (0)

Logic Level High (1)

Sport 0 Data Channel A

Sport 0 Data Channel B

Sport 1 Data Channel A

Sport 1 Data Channel B

Sport 2 Data Channel A

Sport 2 Data Channel B

Sport 3 Data Channel A

Sport 3 Data Channel B

Sport 4 Data Channel A

Sport 4 Data Channel B

Sport 5 Data Channel A

Sport 5 Data Channel B

Sport 6 Data Channel A

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