Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 969

Table A-80. Group F Sources – Pin Output Enable
Selection Code
000000 (0x0)
000001 (0x1)
000010 (0x2)
000011 (0x3)
000100 (0x4)
000101 (0x5)
000110 (0x6)
000111 (0x7)
001000 (0x8)
001001 (0x9)
001010 (0xA)
001011 (0xB)
001100 (0xC)
001101 (0xD)
001110 (0xE)
001111 (0xF)
010000 (0x10)
010001 (0x11)
010010 (0x12)
010011 (0x13)
010100 (0x14)
010101 (0x15)
010110 (0x16)
010111 (0x17)
011000 (0x18)
011001 (0x19)
ADSP-214xx SHARC Processor Hardware Reference
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Source Signal
LOW
HIGH
MISCA0_O
MISCA1_O
MISCA2_O
MISCA3_O
MISCA4_O
MISCA5_O
SPORT0_CLK_PBEN_O
SPORT0_FS_PBEN_O
SPORT0_DA_PBEN_O
SPORT0_DB_PBEN_O
SPORT1_CLK_PBEN_O
SPORT1_FS_PBEN_O
SPORT1_DA_PBEN_O
SPORT1_DB_PBEN_O
SPORT2_CLK_PBEN_O
SPORT2_FS_PBEN_O
SPORT2_DA_PBEN_O
SPORT2_DB_PBEN_O
SPORT3_CLK_PBEN_O
SPORT3_FS_PBEN_O
SPORT3_DA_PBEN_O
SPORT3_DB_PBEN_O
SPORT4_CLK_PBEN_O
SPORT4_FS_PBEN_O
Registers Reference
Description (Output Source Selection)
Logic Level Low (0)
Logic Level High (1)
Miscellaneous Control A0 Output
Miscellaneous Control A1 Output
Miscellaneous Control A2 Output
Miscellaneous Control A3 Output
Miscellaneous Control A4 Output
Miscellaneous Control A5 Output
SPORT 0 Clock Output Enable
SPORT 0 Frame Sync Output Enable
SPORT 0 Data Channel A Output Enable
SPORT 0 Data Channel B Output Enable
SPORT 1 Clock Output Enable
SPORT 1 Frame Sync Output Enable
SPORT 1 Data Channel A Output Enable
SPORT 1 Data Channel B Output Enable
SPORT 2 Clock Output Enable
SPORT 2 Frame Sync Output Enable
SPORT 2 Data Channel A Output Enable
SPORT 2 Data Channel B Output Enable
SPORT 3 Clock Output Enable
SPORT 3 Frame Sync Output Enable
SPORT 3 Data Channel A Output Enable
SPORT 3 Data Channel B Output Enable
SPORT 4 Clock Output Enable
SPORT 4 Frame Sync Output Enable
A-143