Table of Contents
Advertisement
Features
Table 21-1. TWI Specifications (Cont'd)
Feature
Access Type
Data Buffer
Core Data Access
DMA Data Access
DMA Channels
DMA Chaining
Boot Capable
Local Memory
Clock Operation
Features
The TWI is fully compatible with the widely used I
was designed with a high level of functionality and is compatible with
multimaster, multislave bus configurations. To preserve processor band-
width, the TWI controller can be set up and a transfer initiated with
interrupts only. This allows the processor to service FIFO buffer data
reads and writes. Protocol-related interrupts are optional. The TWI mas-
ter controller includes the features described in the list that follows.
• Simultaneous master and slave operation on multiple device
systems
• Support for multimaster data arbitration
• 7-bit addressing
• 100K bits/second and 400K bits/second data rates
• General call address support
21-2
www.BDTIC.com/ADI
Availability
Yes
Yes
No
N/A
N/A
No
No
f
PCLK
ADSP-214xx SHARC Processor Hardware Reference
2
C bus standard. It
Advertisement
Chapters
Table of Contents
