Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 545

Debug Features
The following sections describe the features available for debugging the
IDP.
Status register Debug
The core may also write to the FIFO. When it does, the audio data word is
pushed into the input side of the FIFO (as if it had come from the SRU
on the channel encoded in the three LSBs). This can be useful for verify-
ing the operation of the FIFO, the DMA channels, and the status portions
of the IDP. The
read/write index pointers from FIFO.
Buffer Hang Disable
The bit in
IDP_BHD
there is no data in the FIFO, reading the
to hang. This condition continues until the FIFO contains valid data. Set-
ting the
IDP_BHD
an empty
IDP_FIFO
under the conditions described previously.
If the bit (bit 4 in the
IDP_BHD
read more data than is available in the FIFO results in a core hang.
Shadow Registers
The DAI interrupt controller contains shadow registers to simplify debug
techniques since these register are not updated. A read of the
DAI_IMASK_x_SH
register. Reading these DAI shadow registers
DAI_IMASK_x
(
DAI_IMASK_x_SH
registers.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register returns the current state of the
IDP_STAT1
is used for buffer hang disable control. When
IDP_CTL0
bit (= 1) prevents the core from hanging on reads from
register. Clearing this bit (= 0) causes the core to hang
IDP_CTL0
register provides the same data as a read of the
) does not destroy the contents of the
Input Data Port
register causes the core
IDP_FIFO
register) is not set, attempts to
DAI_IMASK_x
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