Chained Dma - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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Programming Models

4. If scatter/gather DMA is desired, program additional writes to the

5. Enable DMA using the

desired, set the

flushed using the

Once the DMA control register is initialized, the DMA engine fetches the

DMA descriptors from the address pointed to by

descriptors are fetched then the DMA (or the tap list DMA) process starts.

Once the DMA (or tap list DMA) is complete, the new DMA descriptors

are loaded and the process is repeated until

tion interrupt is generated at the end of each DMA block or at the end of

entire chained DMA, depending on the

Chained DMA

Use the following procedure to set up and run a chained DMA on the

external port.

1. Clear the chain pointer register.

2. Configure the

wait states, the data bus width, and so on. Configure the

ister to enable the SDRAM/DDR2, configure the desired clock and

timing settings, data bus width, and other parameters.

3. Initialize the

required after the end of each DMA block. Set the

ferent DMA direction is required in conjunction with the

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bit. It is advised that the DMA FIFOs are

bit when DMA is enabled.

registers to enable the AMI, set the desired

ADSP-214xx SHARC Processor Hardware Reference

bit, and set the transfer direction

registers. If scatter/gather DMA is

. Once the DMA

= 0x0. A DMA comple-

bit setting.

bit if interrupts are

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