Access Completion; Internal Transfer Completion - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Table of Contents

corresponding status register (

the interrupt bits. Read of the status register when an interrupt occurs

causes the core to hang till the interrupt bits are set in the status register.

Otherwise simultaneous read of the status register and updating of the sta-

tus register will result in loss of information. This hang cannot be

overridden with the

Access Completion

An external transfer complete interrupt is generated by the transmitter

once the external transfer is completed by setting bit 12

EXTTXFR_DONE_MSK

interrupt is generated when the transmitter FIFO is empty and the last

byte has been transmitted. Also, when DMA is enabled, the DMA engine

checks if DMA has been completed. (If

enabled, the DMA engine also checks if

This interrupt performs like previous SHARC processors where an inter-

nal transfer complete interrupt is generated by the transmitter once the

word count is zero by setting bit 10 (

When DMA is not enabled, this interrupt is generated when the word

count is zero. Also, when DMA is enabled, the DMA engine checks if

DMA has been completed. (If

DMA engine also checks if

For correct operation, programs should not perform simultaneous

reads and updates of the status register as this results in loss of

information. When an interrupt occurs, reads of the status register

cause the core to hang until the interrupt bits are set in the status

www.BDTIC.com/ADI

). Reading the status register clears

DMACH_IRPT_MSK

is zero, and chaining is enabled, the

also is zero.)

ADSP-214xx SHARC Processor Hardware Reference

is zero, and chaining is

also is zero.)

Table of Contents