Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 319

1. Configure the
accelerator.
2. Program the
= N/16
VDIM
LOG2VDIM
= 0
HDIM
LOG2HDIM
FFT_RPT
FFT_CPACKIN/FFT_CPACKOUT
input/output data is packed into complex words or sent/received
data is real or imaginary.
3. Set (=1) the
imum of 4
4. Program the
FFT_RST
= 1
FFT_EN
FFT_START
FFT_DMAEN
FFT_DEBUG
5. Configure a coefficient DMA to read N complex twiddle factors
from the coefficient buffer into the accelerator (total of 2N 32- bit
words) and wait until the DMA is complete (or chain DMA in Step
4). This step is not needed if twiddles are already in the coefficient
memory of the accelerator.
6. Configure a data DMA to read N complex data points from the
input buffer into the accelerator (total of 2N 32-bit words).
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bits in the
ACCSEL
register with:
FFTCTL2
= Log2(N)
= 0
= 1
bit in the
FFT_RST
cycles.
CCLK
register with:
FFTCTL1
= 0
= 1
= 1
= 0
FFT/FIR/IIR Hardware Modules
register to select the FFT
PMCTL1
= 0 or 1 depending on whether
register and wait for a min-
FFTCTL1
6-23