Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 723

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transmitter transmits the

transmission mode, the parity select controls and the word length select do

not have any effect.

For the receiver, set the

) to enable address detection.

If the received ninth bit is high, the received word is shifted from the

buffer to find out if the device is being addressed. If the device is

being addressed, the address enable (

and address bytes to be read into the receive buffer.

During the 9 bit transmission mode parity has to be calculated in software

to detect errors. The reception may be stopped when the receiver receives

another address which is different from its own.

In 9-bit mode, the address detect interrupt can be generated whenever the

receiver gets an address word, irrespective of the packing mode. This helps

programs respond to an address word immediately. The program is

expected to take into account these features when using packed mode.

Programs must use care when using the packing feature in 9-bit

transmission mode.

• Programs should write the

an address is received. This starts the reception of the following

data from the lower half-word of the

• The address-detect interrupt is generated whenever the UART

receiver receives an address, irrespective of the packing. The DR bit

is in the lower (

ister must be read before reading the

ADSP-214xx SHARC Processor Hardware Reference

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bit instead of the parity bit. During 9-bit

buffer which generates an interrupt. Read the

= 0) or higher half-word (

UART Port Controller

bit) is cleared to allow data

bit (bit 1) with a 1 each time

= 1). The LSR reg-

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