Delay Line Dma - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

4. If circular buffering is needed, use the corresponding TCB storage.
5. Enable DMA using the
If circular buffering is required, set the
ters. It is advised that programs flush the DMA FIFOs using the
bit when DMA is enabled.
DFLSH
Once the DMA control register is initialized, the DMA controller fetches
the DMA descriptors from the address pointed to by the external port
chain pointer register (
Once the DMA descriptors are fetched, the normal DMA process starts.
Upon completion, new DMA descriptors are loaded and the process is
repeated until
CPEP
the end of each DMA block or at the end of an entire chained DMA,
depending on the

Delay Line DMA

1. Configure the
AMI, data bus width and other parameters.
2. Initialize the
required after the end of each delay line DMA block.
3. Enable DMA (
required in the
FIFO (
DFLSH
is required (which is normally the case) enable it by setting the
bit.
CBEN
Once the DMA control register is initialized the DMA engine fetches the
DMA descriptors from the address pointed to by the
the delay line DMA access is complete, the new DMA descriptors are
loaded and the process is repeated until
ADSP-214xx SHARC Processor Hardware Reference
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, bit, set chaining using the
DMAEN
).
CPEP
= 0x0. A DMA completion interrupt is generated at
bit setting.
PCI
register with the desired wait states, enable
AMICTLx
register and set the
CPEP
), delay line DMA (
DMAEN
register. Programs should flush the DMA
DMACx
) along with enabling the DMA. If circular buffering
External Port
bit in the
CBEN
bit if interrupts are
PCI
), chaining (
DLEN
register. Once
CPEP
= 0x0. A DMA completion
CPEP
bit.
CHEN
regis-
DMACx
) if
CHEN
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