Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 914

Peripheral Registers
31 30
15
IIR_RND (16–14)
Rounding Mode
IIR_FORTYBIT
40-Bit Floating-Point Select
IIR_CCINTR
Channel Complete Interrupt
IIR_SS
Save State
Figure A-40. IIRCTL1 Register
Table A-52. IIRCTL1 Register Bit Descriptions (RW)
Bits
0
5–1
7–6
8
9
10
A-88
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29 28 27 26 25 24
14 13 12 11 10 9 8
Name Description
IIR_EN IIR Enable.
0 = IIR disabled
1 = IIR enabled
IIR_NCH Number of Channels. Programmable between 0–23
Channels = NCH + 1
Reserved
IIR_DMAEN DMA Enable.
0 = Disable
1 = Enable
IIR_CAI Channel Auto Iterate.
0 = Processing stops once all channels are over
1 = Moves to first channel and continues processing in a
loop when all channels are over
IIR_SS Save State. Stores the Dk registers settings into local mem-
ory.
ADSP-214xx SHARC Processor Hardware Reference
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
IIR_RND (16–14)
Rounding Mode Select
For Floating-point Mode
IIR_EN
Accelerator Enable
NCH (5–1)
Number of Channels
IIR_DMAEN
DMA Enable
IIR_CAI
Channel Auto Iterate