Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 85

Table 2-4. Count Registers (Cont'd)
Register Name
ICIIR
CCIIR
OCIIR
ICFFT
OCFFT
ICMTMW
ICMTMR
ICEP0–1
ECEP0–1
Chain pointer registers. These registers, shown in
starting address of the TCB (parameter register values) for the next DMA
operation on the corresponding channel. These registers also control
whether the I/O processor generates an interrupt when the current DMA
process ends.

For information on transfer control blocks (TCBs), see
Chaining" on page
Table 2-5. Chain Pointer Registers
Register Name
CPSP0–7A
CPSP0–7B
CPSPI
CPSPIB
CPLB0–1
CPUART0RX
CPUART0TX
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Width (Bits) Description
16 Accelerator IIR data input
16 Accelerator IIR coeff input
16 Accelerator IIR output
16 Accelerator FFT input
16 Accelerator FFT output
16 MTM Write
16 MTM Read
16 External Port
16 External Port (external)
2-32.
Width (Bits) Description
28 SPORTA
28 SPORTB
20 SPI
20 SPIB
20 Link Port
20 UART0 Receiver
20 UART0 Transmitter
I/O Processor
Table 2-5, hold the
"DMA
2-7