Ami Data Throughput; Sdram Throughput; Throughput Conditional Instructions - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

AMI Data Throughput

The AMI data throughput is shown in
Table 3-29. Read/Write Throughput
1 8-Bit I/O
Access
Write 32-bit word per 12 cycles
Read 32-bit word per 12 cycles
1 Throughput for minimum wait states of 2 with no idle and hold cycles.

SDRAM Throughput

Table 3-30 provides information needed to configure the SDRAM inter-
face for the desired throughput.
Table 3-30. SDRAM Data Throughput
Access
Sequential uninterrupted reads
Any writes
Non sequential
uninterrupted reads
1 Optimization enabled, first data of a sequential read takes 7 cycles for CL =2 and 8 cycles for
CL = 3, thereafter it is one word per two cycles.

Throughput Conditional Instructions

A conditional read/write may take 1
aborted, respectively).
Access Restrictions" on page 3-132.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Table
Page
Same
Same
Same
PCLK
For more information, see "External Memory
External Port
3-29.
16-Bit I/O
32-bit word per 6 cycles
32-bit word per 6 cycles
Throughput per SDCLK (16-Bit Data)
One word per two cycles
2 cycles
7 cycles
cycle (access made and access
1
3-117